NTTFS5C471NLTAG

DATA SHEET www.onsemi.com MOSFET – Power, Single N-Channel V(BR)DSS RDS(on) MAX 9.0 mW @ 10 V 40 V 40 V, 9.0 mW, 41 A 15.5 mW @ 4.5 V NTTFS5C471NL 41 A N−Channel D (5 − 8) Features • • • • ID MAX Small Footprint (3.3 x 3.3 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses These Devices are Pb−Free and are RoHS Compliant G (4) S (1, 2, 3) MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 40 V Gate−to−Source Voltage VGS ±20 V ID 41 A Continuous Drain Current RqJC (Notes 1, 2, 3, 4) TC = 25°C Power Dissipation RqJC (Notes 1, 2, 3) Continuous Drain Current RqJA (Notes 1, 3, 4) Steady State TC = 100°C TC = 25°C Power Dissipation RqJA (Notes 1, 3) Pulsed Drain Current Steady State PD W 30 ID 10 PD W 3.0 163 A TJ, Tstg −55 to +175 °C IS 24 A Single Pulse Drain−to−Source Avalanche Energy (IL(pk) = 2.2 A) EAS 66 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Source Current (Body Diode) 471L AYWWG G D D D D 2.0 IDM Operating Junction and Storage Temperature Range 1 S S S G A 12 TA = 100°C TA = 25°C, tp = 10 ms MARKING DIAGRAM 15 TA = 100°C TA = 25°C WDFN8 (m8FL) CASE 511AB 27 TC = 100°C TA = 25°C 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 471L A Y WW G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. THERMAL RESISTANCE MAXIMUM RATINGS (Note 1) Parameter Symbol Value Unit Junction−to−Case − Steady State (Note 3) RqJC 5.2 °C/W Junction−to−Ambient − Steady State (Note 3) RqJA 50 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Psi (Y) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface. 3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 4. Continuous DC current rating. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2017 September, 2023 − Rev. 4 1 Publication Order Number: NTTFS5C471NL/D NTTFS5C471NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min V(BR)DSS VGS = 0 V, ID = 250 mA 40 Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current VGS = 0 V, VDS = 40 V V TJ = 25°C 10 TJ = 125°C 250 100 mA IGSS VDS = 0 V, VGS = 20 V nA Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 20 mA 1.7 2.2 V Drain−to−Source On Resistance RDS(on) VGS = 10 V, ID = 10 A 7.4 9.0 mW VGS = 4.5 V, ID = 10 A 12.3 15.5 VDS = 15 V, ID = 20 A 36 S 660 pF ON CHARACTERISTICS (Note 5) Forward Transconductance gFS 1.2 CHARGES AND CAPACITANCES Ciss Input Capacitance Output Capacitance Coss Reverse Transfer Capacitance Crss Output Charge QOSS Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD VGS = 0 V, f = 1.0 MHz, VDS = 25 V 270 VGS = 0 V, VDD = 20 V 9.0 nC 5.5 nC 1.4 nC VGS = 4.5 V, VDS = 20 V, ID = 20 A 12 2.6 1.8 Total Gate Charge QG(TOT) VGS = 10 V, VDS = 20 V, ID = 20 A 12 nC Gate Resistance RG TA = 25°C 1.3 W 9.0 ns SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) VGS = 4.5 V, VDS = 20 V, ID = 20 A, RG = 1.0 W tf 49 20 6 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 10 A TJ = 25°C 0.8 TJ = 125°C 0.7 tRR ta tb 23 VGS = 0 V, dlS/dt = 100 A/ms, IS = 20 A QRR 1.2 V ns 11 11 10 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 6. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NTTFS5C471NL TYPICAL CHARACTERISTICS 60 60 VDS = 10 V 50 3.8 V 30 3.6 V ID, DRAIN CURRENT (A) 40 3.4 V 20 3.2 V 10 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) 4.0 V 0 0.5 1.0 1.5 2.0 2.5 3.0 40 30 20 TJ = 25°C 10 TJ = 125°C 1 3 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 45 40 35 30 25 20 15 10 5 0 4 5 6 7 8 9 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 18 TJ = 25°C 16 VGS = 4.5 V 14 12 10 VGS = 10 V 8 6 4 10 15 20 25 35 30 40 45 50 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.0 100K VGS = 10 V ID = 10 A TJ = 175°C IDSS, LEAKAGE (nA) 1.5 1.0 0.5 0 −50 5 4 VGS, GATE−TO−SOURCE VOLTAGE (V) TJ = 25°C ID = 10 A RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE TJ = −55°C 2 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 50 3 50 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) ID, DRAIN CURRENT (A) 10 V to 4.5 V −25 0 25 50 75 100 125 150 175 10K TJ = 125°C 1K TJ = 85°C 100 10 5 10 15 20 25 30 35 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 40 NTTFS5C471NL TYPICAL CHARACTERISTICS VGS, GATE−TO−SOURCE VOLTAGE (V) 1000 C, CAPACITANCE (pF) CISS COSS 100 10 CRSS VGS = 0 V TJ = 25°C f = 1 MHz 1 5 0 15 10 20 25 30 35 40 7 6 5 QGD QGS 4 3 VDS = 20 V ID = 20 A TJ = 25°C 2 1 0 2 0 4 6 10 8 12 Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total Charge VGS = 0 V IS, SOURCE CURRENT (A) td(off) t, TIME (ns) 8 QG, TOTAL GATE CHARGE (nC) tr td(on) 10 tf VGS = 4.5 V VDS = 20 V ID = 20 A 1 10 10 1 100 TJ = 125°C 0.3 0.4 TJ = 25°C TJ = −55°C 0.5 0.6 0.7 0.8 0.9 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 100 1000 TJ (initial) = 25°C 100 10 10 TC = 25°C VGS ≤ 10 V Single Pulse 1 0.1 IPEAK, (A) ID, DRAIN CURRENT (A) 9 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 100 1 10 10 ms 0.5 ms 1 ms 10 ms RDS(on) Limit Thermal Limit Package Limit 0.1 1 TJ (initial) = 100°C 1 10 0.1 100 1E−5 1E−4 1E−3 VDS, DRAIN−TO−SOURCE VOLTAGE(V) TIME IN AVALANCHE (s) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. IPEAK vs. Time in Avalanche www.onsemi.com 4 1E−2 NTTFS5C471NL TYPICAL CHARACTERISTICS RqJA(t), TRANSIENT THERMAL IMPEDANCE (°C/W) 100 50% Duty Cycle 20% 10% 5% 2% 1 1% 10 0.1 Single Pulse 0.01 0.000001 TA = 25°C 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 t, RECTANGULAR PULSE DURATION (s) RqJC(t), TRANSIENT THERMAL IMPEDANCE (°C/W) Figure 13. Thermal Response 10 50% Duty Cycle 1 20% 10% 5% 2% 1% 0.1 Single Pulse TC = 25°C 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 t, RECTANGULAR PULSE DURATION (s) Figure 14. Thermal Response DEVICE ORDERING INFORMATION Device NTTFS5C471NLTAG Marking Package Shipping† 471L WDFN8 (Pb−Free) 1500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFN8 3.3x3.3, 0.65P CASE 511AB ISSUE D 1 DATE 23 APR 2012 SCALE 2:1 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 0.20 C D A D1 B 2X 0.20 C 8 7 6 5 4X E1 E q c 1 2 3 4 A1 TOP VIEW 0.10 C A e SIDE VIEW 0.10 8X b C A B 0.05 C 4X DETAIL A 8X e/2 1 0.42 4 INCHES NOM 0.030 −−− 0.012 0.008 0.130 BSC 0.116 0.120 0.078 0.083 0.130 BSC 0.116 0.120 0.058 0.063 0.009 0.012 0.026 BSC 0.012 0.016 0.026 0.032 0.012 0.017 0.002 0.005 0.055 0.059 0_ −−− MIN 0.028 0.000 0.009 0.006 MAX 0.031 0.002 0.016 0.010 0.124 0.088 0.124 0.068 0.016 0.020 0.037 0.022 0.008 0.063 12 _ 0.65 PITCH PACKAGE OUTLINE 4X 0.66 M E3 8 5 D2 BOTTOM VIEW 1 3.60 L1 GENERIC MARKING DIAGRAM* XXXXX A Y WW G MILLIMETERS MIN NOM MAX 0.70 0.75 0.80 0.00 −−− 0.05 0.23 0.30 0.40 0.15 0.20 0.25 3.30 BSC 2.95 3.05 3.15 1.98 2.11 2.24 3.30 BSC 2.95 3.05 3.15 1.47 1.60 1.73 0.23 0.30 0.40 0.65 BSC 0.30 0.41 0.51 0.65 0.80 0.95 0.30 0.43 0.56 0.06 0.13 0.20 1.40 1.50 1.60 0_ −−− 12 _ SOLDERING FOOTPRINT* L G SEATING PLANE DETAIL A K E2 C 6X 0.10 C DIM A A1 b c D D1 D2 E E1 E2 E3 e G K L L1 M q XXXXX AYWWG G 0.75 2.30 0.57 0.47 2.37 3.46 DIMENSION: MILLIMETERS = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON30561E WDFN8 3.3X3.3, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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