DATA SHEET
www.onsemi.com
Low Current LED Driver
NUD4011
8
This device is designed to replace discrete solutions for driving
LEDs in AC/DC high voltage applications (up to 200 V). An external
resistor allows the circuit designer to set the drive current for different
LED arrays. This discrete integration technology eliminates individual
components by combining them into a single package, which results in
a significant reduction of both system cost and board space. The
device is a small surface mount package (SO−8).
1
SO−8
CASE 751
MARKING DIAGRAM
8
Features
•
•
•
•
Supplies Constant LED Current for Varying Input Voltages
External Resistor Allows Designer to Set Current – up to 70 mA
Offered in Surface Mount Package Technology (SO−8)
This is a Pb−Free Device
Benefits
•
•
•
•
Maintains a Constant Light Output During Battery Drain
One Device can be used for Many Different LED Products
Reduces Board Space and Component Count
Simplifies Circuit and System Designs
1
4011
AYWWG
G
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
AND SCHEMATIC
Typical Applications
• Portables: For Battery Back−up Applications, also Simple Ni−CAD
•
•
Battery Charging
Industrial: General Lighting Applications and Small Appliances
Automotive: Tail Lights, Directional Lights, Back−up Light,
Dome Light
Vin
1
8
Iout
Boost
2
7
Iout
Rext
3
6
Iout
PWM
4
5
Iout
PIN FUNCTION DESCRIPTION
Pin
Symbol
Description
1
Vin
2
Boost
This pin may be used to drive an external transistor
as described in the App Note AND8198/D.
3
Rext
An external resistor between Rext and Vin pins sets
different current levels for different application needs
4
PWM
For high voltage applications (higher than 48 V),
pin 4 is connected to the LEDs array.
For low voltage applications (lower than 48 V), pin 4
is connected to ground.
5, 6, 7, 8
Iout
The LEDs are connected from these pins to ground
Current
Set Point
Positive input voltage to the device
© Semiconductor Components Industries, LLC, 2006
November, 2022 − Rev. 4
1
ORDERING INFORMATION
Device
NUD4011DR2G
Package
Shipping†
SO−8
2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NUD4011/D
NUD4011
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Symbol
Value
Unit
Input Voltage
Vin
200
V
Output Current
(For Vdrop ≤ 16 V) (Note 1)
Iout
70
mA
Output Voltage
Vout
198
V
Human Body Model (HBM)
ESD
500
V
Rating
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Vdrop = Vin – 0.7 V − VLEDs.
THERMAL CHARACTERISTICS
Characteristic
Symbol
Value
Unit
Operating Ambient Temperature
TA
−40 to +125
°C
Maximum Junction Temperature
TJ
150
°C
TSTG
−55 to +150
°C
PD
1.13
9.0
W
mW/°C
Thermal Resistance, Junction–to–Ambient (Note 2)
RJA
110
°C/W
Thermal Resistance, Junction–to–Lead (Note 2)
RJL
77
°C/W
Storage Temperature
Total Power Dissipation (Note 2)
Derating above 25°C (Figure 3)
2. Mounted on FR−4 board, 2 in sq pad, 1 oz coverage.
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Output Current1 (Note 3)
(Vin = 120 Vdc, Rext = 24 , VLEDs = 90 V)
Iout1
26.0
27.5
29.5
mA
Output Current2 (Note 3)
(Vin = 200 Vdc, Rext = 68 , VLEDs = 120 V)
Iout2
11.5
14.0
15.5
mA
Bias Current
(Vin = 120 Vdc, Rext = Open, Rshunt = 80 k)
IBias
−
1.1
2.0
mA
Voltage Overhead (Note 4)
Vover
5.0
−
−
V
Characteristic
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Device’s pin 4 connected to the LEDs array (as shown in Figure 5).
4. Vover = Vin – VLEDs.
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2
NUD4011
TYPICAL PERFORMANCE CURVES
(TA = 25°C UNLESS OTHERWISE NOTED)
1000
0.9
0.8
0.7
100
Rext,
Vsense (V)
0.6
10
0.5
0.4
0.3
0.2
0.1
1
1
100
10
0.0
−40 −25 −10 5
1000
IOUT (mA)
Figure 1. Output Current (IOUT)
vs. External Resistor (Rext)
Figure 2. Vsense vs. Junction Temperature
1.2
PD, POWER DISSIPATION (W)
OUTPUT CURRENT, NORMALIZED
1.200
1.000
0.800
0.600
0.400
0.200
0.000
25
20 35 50 65 80 95 110 125 140 155
TJ, JUNCTION TEMPERATURE (°C)
1.0
0.8
0.6
0.4
0.2
TA, AMBIENT TEMPERATURE (°C)
0.0
−40 −25 −10 5 20 35 50 65 80 95 110 125 140 155
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Total Power Dissipation (PD)
vs. Ambient Temperature (TA)
Figure 4. Current Regulation vs. Junction
Temperature
35
45
55
65
75
85
95
105 115 125
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3
NUD4011
APPLICATION INFORMATION
Design Guide for DC Applications
NUD4011
Vin
1. Define LED’s current:
A ILED = 30 mA
Boost
2. Calculate Resistor Value for Rext:
A Rext = Vsense (see Figure 2) / ILED
B Rext = 0.7(TJ = 25 °C) / 0.030 = 24
Rext
PWM
3. Define Vin:
A Per example in Figure 5, Vin = 120 Vdc
4. Define VLED @ ILED per LED supplier’s data
sheet: per example in Figure 5,
A VLED = 3.0 V (30 LEDs in series)
B VLEDs = 90 V
1
8
2
7
3
4
Current
Set Point
6
5
120 V
Iout
Iout
Iout
Iout
LED1
LED2
5. Calculate Vdrop across the NUD4001 device:
A Vdrop = Vin – Vsense – VLEDs
B Vdrop = 120 V – 0.7 V – 90 V
C Vdrop = 29.3 V
LED30
6. Calculate Power Dissipation on the NUD4001
device’s driver:
A PD_driver = Vdrop * Iout
B PD_driver = 29.3 V 0.030 A
C PD_driver = 0.879 W
Figure 5. 120 V Application
(Series LED’s Array)
7. Establish Power Dissipation on the NUD4001
device’s control circuit per below formula:
A PD_control = (Vin – 1.4 – VLEDs)@ / 20,000
B PD_control = 0.040 W
8. Calculate Total Power Dissipation on the device:
A PD_total = PD_driver + PD_control
B PD_total = 0.879 W + 0.040 W = 0.919 W
9. If PD_total > 1.13 W (or derated value per
Figure 3), then select the most appropriate
recourse and repeat steps 1−8:
A Reduce Vin
B Reconfigure LED array to reduce Vdrop
C Reduce Iout by increasing Rext
D Use external resistors or parallel device’s
configuration
10. Calculate the junction temperature using the
thermal information on Page 8 and refer to
Figure 4 to check the output current drop due to
the calculated junction temperature. If desired,
compensate it by adjusting the value of Rext.
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4
NUD4011
APPLICATION INFORMATION (CONTINUED)
Design Guide for AC Applications
Vin
Full
Bridge
Rectifier 1
1. Define LED’s current:
A ILED = 30 mA
2. Define Vin:
A Per example in Figure 5, Vin = 120 Vac
2
1
3
4
+
−
120 Vac
60 Hz
Iout
2
3
Iout
8
Boost
Rext
3. Define VLED @ ILED per LED supplier’s data
sheet:
A Per example in Figure 6,
VLED = 3.0 V (30 LEDs in series)
VLEDs = 90 V
NUD4011
7
Current
Set Point
PWM
4
Iout
6
Iout
5
LED1
4. Calculate Resistor Value for Rext:
The calculation of the Rext for AC applications is
totally different than for DC. This is because
current conduction only occurs during the time
that the ac cycles’ amplitude is higher than VLEDs.
Therefore Rext calculation is now dependent on the
peak current value and the conduction time.
A Calculate for VLEDs = 90 V:
V = Vpeak Sin
Ǹ2) Sin
90 V = (120
LED2
LED30
Figure 6. 120 Vac Application
(Series LED’s array)
= 32.027°
B Calculate conduction time for = 32.027°. For a
sinuousoidal waveform Vpeak happens at
= 90°. This translates to 4.165 ms in time for a
60 Hz frequency, therefore 32.027° is 1.48 ms and
finally:
Conduction time
= (4.165 ms – 1.48 ms) 2
6. Calculate Power Dissipation on the NUD4011
device’s driver:
A PD_driver = Vdrop * I(avg)
B PD_driver = 29.3 V 0.030 A
C PD_driver = 0.879 W
7. Establish Power Dissipation on the
NUD4011device’s control circuit per below
formula:
A PD_control = (Vin – 1.4 – VLEDs)@ / 20,000
B PD_control = 0.040 W
= 5.37 ms
C Calculate the Ipeak needed for I(avg) = 30 mA
Since a full bridge rectifier is being used (per
Figure 6), the frequency of the voltage signal
applied to the NUD4011 device is now 120 Hz.
To simplify the calculation, it is assumed that the
120 Hz waveform is square shaped so that the
following formula can be used:
I(avg) = Ipeak duty cycle;
If 8.33 ms is 100% duty cycle, then 5.37 ms is
64.46%, then:
Ipeak = I(avg) / duty cycle
Ipeak = 30 mA / 0.645 = 46 mA
D Calculate Rext
Rext = 0.7 V / Ipeak
Rext = 15.21
8. Calculate Total Power Dissipation on the device:
A PD_total = PD_driver + PD_control
B PD_total = 0.879 W + 0.040 W = 0.919 W
9. If PD_total > 1.13 W (or derated value per
Figure 3), then select the most appropriate
recourse and repeat steps 1−8:
A Reduce Vin
B Reconfigure LED array to reduce Vdrop
C Reduce Iout by increasing Rext
D Use external resistors or parallel device’s
configuration
10. Calculate the junction temperature using the
thermal information on Page 8 and refer to
Figure 4 to check the output current drop due to
the calculated junction temperature. If desired,
compensate it by adjusting the value of Rext.
5. Calculate Vdrop across the NUD4011 device:
A Vdrop = Vin – Vsense – VLEDs
B Vdrop = 120 V – 0.7 V – 90 V
C Vdrop = 29.3 V
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5
NUD4011
TYPICAL APPLICATION CIRCUITS
NUD4011
Switch
Vin
35 , 1/4 W
Boost
Rext
PWM
+
−
1
8
2
7
Current
Set Point
3
6
4
5
Iout
Iout
Iout
Iout
120 Vdc
LED1
LED2
LED30
Figure 7. 120 Vdc Application Circuit for a Series Array of 30 LEDs (3.0 V, 20 mA)
NUD4011
Vin
Full
Bridge
Rectifier
Switch
+
2
VARISTOR
200 V
−
1
30 , 1/4 W
3
Boost
Rext
PWM
4
1
8
2
7
3
4
Current
Set Point
6
5
Iout
Iout
Iout
Iout
120 Vac 60 Hz
LED1
LED2
LED30
Figure 8. 120 Vac Application Circuit for a Series Array of 30 LEDs (3.0 V, 20 mA)
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6
NUD4011
TYPICAL APPLICATION CIRCUITS (continued)
Switch
35 , 1/4 W
NUD4011
Vin
Boost
Rext
PWM
120 Vdc
8
2
7
Current
Set Point
3
6
4
+
−
1
5
Rshunt
80 k, 1/4 W
1.0 k
+
−
Iout
Iout
Iout
Iout
LED1
Q1
200 V
LED2
PWM /
ENABLE
LED30
Figure 9. 120 Vdc Application with PWM / Enable Function, 30 LEDs in Series (3.0 V, 20 mA)
NUD4011
Vin
Full
Bridge
Rectifier
Switch
+
2
VARISTOR
200 V
−
120 Vac 60 Hz
1
35 , 1/4 W
3
4
Boost
Rext
200 V
Electrolytic
Cap
PWM
1
8
2
7
3
4
Rshunt
80 k, 1/4 W
1.0 k
+
PWM /
ENABLE
−
Q1
200 V
Current
Set Point
6
5
Iout
Iout
Iout
Iout
LED1
LED2
LED30
Figure 10. 120 Vac Application with PWM / Enable Function, 30 LEDs in Series (3.0 V, 20 mA)
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7
NUD4011
THERMAL INFORMATION
NUD4011 Power Dissipation
reduce the thermal resistance. Figure 11 shows how the
thermal resistance changes for different copper areas.
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad®. Using a
board material such as Thermal Clad or an aluminum core
board, the power dissipation can be even doubled using the
same footprint.
The power dissipation of the SO−8 is a function of the pad
size. This can vary from the minimum pad size for soldering
to a pad size given for maximum power dissipation. Power
dissipation for a surface mount device is determined by
TJ(max), the maximum rated junction temperature of the die,
RJA, the thermal resistance from the device junction to
ambient, and the operating temperature, TA. Using the
values provided on the data sheet for the SO−8 package, PD
can be calculated as follows:
180
160
T
* TA
PD + Jmax
RJA
JA (°C/W)
140
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 1.13 W.
120
100
80
PD + 150° C * 25° C + 1.13 W
110° C
60
The 110°C/W for the SO−8 package assumes the use of a
FR−4 copper board with an area of 2 square inches with 2 oz
coverage to achieve a power dissipation of 1.13 W. There are
other alternatives to achieving higher dissipation from the
SOIC package. One of them is to increase the copper area to
0
1
2
3
4
5
6
7
8
10
9
BOARD AREA (in2)
Figure 11. qJA versus Board Area
250
1S −36.9 sq. mm −0.057 in sq.
1S −75.8 sq. mm −0.117 in sq.
200
R() (C°/W)
1S −150.0 sq. mm −0.233 in sq.
150
1S −321.5 sq. mm −0.498 in sq.
1S −681.0 sq. mm −1.056 in sq.
100
1S −1255.0 sq. mm −1.945 in sq.
50
0
0.000001
0.00001
0.0001
0.001
0.1
0.01
1
TIME (sec)
Figure 12. Transient Thermal Response
Thermal Clad is a registered trademark of the Bergquist Company.
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8
10
100
1000
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
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are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
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SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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