NUF9002FC
Low Capacitance 10 Line
EMI Filter with ESD
Protection
This device is a ten−line EMI filter array for wireless applications.
Greater than −25 dB attenuation is obtained at frequencies from
900 MHz to 3.0 GHz. ESD protection is provided across all
capacitors.
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LOW−PASS FILTER
INPUT
OUTPUT
Features
• EMI Filtering and ESD Protection
• Integration of 50 Discretes
• Provides Protection for IEC61000−4−2 (Level 4)
•
•
•
•
RI/O = 100 W
Cinput = 28 pF
♦ 8.0 kV (Contact)
Flip−Chip Package
Moisture Sensitivity Level 1
ESD Rating: Machine Model = C; Human Body Model = 3B
Pb−Free Package is Available*
A1
• Reduces EMI/RFI Emissions on a Data Line
• Integrated Solution Offers Cost and Space Savings
• Reduces Parasitic Inductances Which Offer a More “Ideal” Low Pass
NUF9002 = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Filter Response
Integrated Solution Improves System Reliability
PIN CONFIGURATION
(Ball Side)
Applications
•
•
•
•
LCD for Cell Phones and PDAs
Computers and Printers
Communication Systems
MP3 Players
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Symbol
Value
Unit
VPP
8.0
kV
Steady−State Power per Resistor
PR
100
mW
Steady−State Power per Package
PT
200
mW
Operating Temperature Range
TOP
−40 to +85
°C
Storage Temperature Range
TSTG
−55 to +150
°C
TJ
+125
°C
Rating
ESD Discharge
IEC61000−4−2
Contact Discharge
Junction Temperature
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 1
NUF9002
AYWWG
G
Flip−Chip
CASE 499G
Benefits
•
ÇÇ
ÇÇ
MARKING DIAGRAM
1
1
2
3
4
5
E
O1
O2
O3
O4
O5
D
O6
O7
O8
O9
O10
C
GND
GND
GND
GND
GND
B
IN6
IN7
IN8
IN9
IN10
A
IN1
IN2
IN3
IN4
IN5
ORDERING INFORMATION
Device
Package
Shipping†
NUF9002FCT1
Flip−Chip
3000 Tape & Reel
NUF9002FCT1G
Flip−Chip
(Pb−Free)
3000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NUF9002FC/D
NUF9002FC
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Maximum Reverse Working Voltage
VRWM
−
−
−
5.0
V
VBR
IR = 1.0 mA
6.0
7.0
8.0
V
IR
VRM = 3.0 V
−
−
0.1
mA
Breakdown Voltage
Leakage Current
Series Resistance
Capacitance
RA
−
85
100
115
W
CLINE 1
f = 1.0 MHz, 0 Vdc
−
28
35
pF
f3dB
(Above this frequency,
appreciable attenuation occurs)
−
110
−
MHz
Cut−Off Frequency
TYPICAL PERFORMANCE CURVE
(TA = 25°C unless otherwise specified)
0
0
−5
−10
−20
−15
S41 (dB)
S21 (dB)
−10
−20
−25
Channel 6 or 10
−30
−30
−40
−50
−35
−40
−60
Channel 2, 3, 4, and 8
−45
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
−70
1.E+07
1.E+08
FREQUENCY (Hz)
Figure 2. Analog Crosstalk Curve
(S41 Measurement)
35
110
108
30
106
25
RESISTANCE (W)
CAPACITANCE (pF)
1.E+10
FREQUENCY (Hz)
Figure 1. Insertion Loss Characteristics
(S21 Measurement)
20
15
10
104
102
100
98
96
94
5
0
1.E+09
92
0
1
2
3
4
90
−40
5
−20
0
20
40
60
80
TEMPERATURE (°C)
REVERSE VOLTAGE (V)
Figure 3. Typical Line Capacitance vs. Reverse
Bias Voltage
Figure 4. Typical Resistance Over Temperature
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2
NUF9002FC
PRINTED CIRCUIT BOARD RECOMMENDATIONS
500 mm Pitch
300 or 350 mm Solder Ball
Parameter
PCB Pad Size
250 mm +25
−0
Pad Shape
Round
Pad Type
NSMD
Solder Mask Opening
350 mm "25
Solder Stencil Thickness
125 mm
Stencil Aperture
250 x 250 mm sq.
Solder Flux Ratio
50/50
Solder Paste Type
No Clean Type 3 or Finer
Trace Finish
OSP Cu
Trace Width
150 mm Max
Copper
Solder mask
NSMD
SMD
Figure 5. NSMD vs. SMD
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3
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
FLIP−CHIP−25 CSP
CASE 499G−01
ISSUE B
DATE 03 MAY 2005
A1
SCALE 4:1
Ç
Ç
4X
0.10 C
PIN A1
LOCATOR
D
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
B
DIM
A
A1
A2
D
E
b
e
D1
E1
E
TOP VIEW
0.10 C
C
A
SEATING
PLANE
GENERIC
MARKING DIAGRAM*
ÇÇ
ÇÇ
A2
SIDE VIEW A1
0.05 C
MILLIMETERS
MIN
MAX
0.700
−−−
0.210
0.270
0.380
0.430
2.650 BSC
2.650 BSC
0.290
0.340
0.500 BSC
2.000 BSC
2.000 BSC
D1
xxxxxxxxxx
AYWW
e
E
D
25 X
b
0.05 C A B
0.03 C
C
E1
xxxxxx
A
Y
WW
B
A
1
2
3
4
5
BOTTOM VIEW
DOCUMENT NUMBER:
DESCRIPTION:
98AON13902D
e
= Specific Device Code
= Assembly Location
= Year
= Work Week
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
FLIP−CHIP−25 CSP, 0.265 *0.265 MM, 0.500 PITCH
PAGE 1 OF 1
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