NVD260N65S3T4G

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Other names and brands may be claimed as the property of others. MOSFET – Power, N-Channel, SUPERFET) III, Easy Drive 650 V, 260 mW, 12 A NVD260N65S3 Features • • • • • Ultra Low Gate Charge & Low Effective Output Capacitance Lower FOM (RDS(on) max. x Qg typ. & RDS(on) max. x EOSS) 100% Avalanche Tested AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant www.onsemi.com VDSS RDS(ON) MAX ID MAX 650 V 260 mW @ 10 V 12 A MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Symbol Value Unit VDSS 650 V Gate−to−Source Voltage − DC VGSS ±30 V Gate−to−Source Voltage − AC (f > 1 Hz) VGSS ±30 V Drain Current − Continuous (TC = 25°C) ID 12 A Drain Current − Continuous (TC = 100°C) ID 7.6 A Drain Current − Pulsed (Note 3) IDM 30 A Power Dissipation (TC = 25°C) PD 90 W Power Dissipation − Derate Above 25°C PD 0.72 W/°C TJ, TSTG −55 to +150 °C Single Pulsed Avalanche Energy (Note 4) EAS 57 mJ Repetitive Avalanche Energy (Note 3) EAR 0.9 mJ MOSFET dv/dt dv/dt 100 V/ns Peak Diode Recovery dv/dt (Note 5) dv/dt 20 V/ns TL 300 °C Symbol Value Unit Thermal Resistance, Junction−to−Case, Max. (Notes 1, 2) RqJC 1.39 °C/W Thermal Resistance, Junction−to−Ambient, Max. (Notes 1, 2, 6) RqJA 40 Operating Junction and Storage Temperature Range Max. Lead Temperature for Soldering Purposes (1/8″ from case for 5 s) D G S POWER MOSFET 4 1 2 MARKING DIAGRAM AYWW V26 0N65S3 THERMAL CHARACTERISTICS Parameter Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The entire application environment impacts the thermal resistance values shown. They are not constants and are only valid for the particular conditions noted. 2. Assembled to an infinite heatsink with perfect heat transfer from the case (assumes 0 K/W thermal interface). 3. Repetitive rating: pulse−width limited by maximum junction temperature. 4. IAS = 2.3 A, RG = 25 W, starting TJ = 25°C. 5. ISD ≤ 6 A, di/dt ≤ 200 A/ms, VDD ≤ 400 V, starting TJ = 25°C. 6. Device on 1 in2 pad 2 oz copper pad on 1.5 x 1.5 in. board of FR−4 material. © Semiconductor Components Industries, LLC, 2020 December, 2020 − Rev. 0 1 3 DPAK CASE 369C A = Assembly Location Y = Year WW = Work Week V260N65S3 = Specific Device Code ORDERING INFORMATION Device NVD260N65S3 Package Shipping† DPAK3 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NVD260N65S3/D NVD260N65S3 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Symbol Test Conditions Min Drain−to−Source Breakdown Voltage BVDSS VGS = 0 V, ID = 1 mA, TJ = 25°C 650 V Drain−to−Source Breakdown Voltage BVDSS VGS = 0 V, ID = 1 mA, TJ = 150°C 700 V Breakdown Voltage Temperature Coefficient DBVDSS/ DTJ ID = 1 mA, Referenced to 25_C Zero Gate Voltage Drain Current IDSS VGS = 0 V, VDS = 650 V Gate−to−Body Leakage Current IGSS VGS = ±30 V, VDS = 0 V VGS(th) VGS = VDS, ID = 0.29 mA DVGS(th)/DTJ VGS = VDS, ID = 0.29 mA −8.9 RDS(on) VGS = 10 V, ID = 6 A 217 gFS VDS = 20 V, ID = 6 A 7.3 S 1042 pF Parameter Typ Max Unit OFF CHARACTERISTICS 660 mV/_C 1 mA ±100 nA 4.5 V 0.77 VDS = 520 V, TC = 125_C ON CHARACTERISTICS Gate Threshold Voltage Threshold Temperature Coefficient Static Drain−to−Source On Resistance Forward Transconductance 2.5 mV/_C 260 mW DYNAMIC CHARACTERISTICS Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Effective Output Capacitance Coss(eff.) VDS = 0 V to 400 V, VGS = 0 V 225 Energy Related Output Capacitance Coss(er.) VDS = 0 V to 400 V, VGS = 0 V 37.5 pF 23.5 nC Total Gate Charge at 10 V QG(TOT) Threshold Gate Charge QG(TH) Gate−to−Source Gate Charge QGS Gate−to−Drain “Miller” Charge QGD Equivalent Series Resistance ESR VGS = 0 V, VDS = 400 V, f = 1 MHz 22.5 3.8 VGS = 10 V, VDS = 400 V, ID = 6 A (Note 7) pF 3.8 6.3 9.8 f = 1 MHz 8.1 W 17.2 ns 13.9 ns 48.3 ns 8.3 ns SWITCHING CHARACTERISTICS Turn-On Delay Time td(on) Turn-On Rise Time tr Turn-Off Delay Time td(off) Turn-Off Fall Time VGS = 10 V, VDD = 400 V, ID = 6 A, Rg = 4.7 W (Note 7) tf SOURCE−DRAIN DIODE CHARACTERISTICS Maximum Continuous Source−to− Drain Diode Forward Current IS Maximum Pulsed Source−to−Drain Diode Forward Current ISM Source−to−Drain Diode Forward Voltage VSD Reverse Recovery Time trr Charge Time ta Discharge Time tb Reverse Recovery Charge Qrr VGS = 0 V VGS = 0 V VGS = 0 V, ISD = 6 A 232 VGS = 0 V, dIF/dt = 100 A/ms, ISD = 6 A 12 A 30 A 1.2 V ns 220 13 2837 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 7. Essentially independent of operating temperature typical characteristics. www.onsemi.com 2 NVD260N65S3 TYPICAL CHARACTERISTICS 100.0 VGS = 10.0 V 8.0 V 7.0 V 10 6.5 V 6.0 V 5.5 V ID, Drain Current (A) ID, Drain Current (A) 40 1 0.1 0.2 10.0 1.0 250 ms Pulse Test TC = 150°C 250 ms Pulse Test TC = 25°C 1 10 VDS, Drain−Source Voltage (V) 0.1 20 Figure 1. On−Region Characteristics 255C 150°C 25°C −55°C 3 6 4 5 7 8 VGS, Gate−Source Voltage (V) 1000 800 600 0 RDS(on), Drain−Source On−Resistance (Normalized) RDS(ON), Drain−Source On−Resistance (W) 5 6 7 8 9 Figure 4. RDS(on) vs. Gate Voltage 3.0 VGS = 20 V 10 20 30 ID, Drain Current (A) 4 VGS, GATE TO SOURCE VOLTAGE (V) VGS = 10 V 0.0 0 TJ = 25°C 200 9 0.6 0.2 TJ = 150°C 400 TC = 25°C 0.4 ID = 6 A 1200 Figure 3. Transfer Characteristics 0.8 1.0 10.0 VDS, Drain−Source Voltage (V) 1400 VDS = 20 V 250 ms Pulse Test 10 1 0.1 Figure 2. On−Region Characteristics 1505C RDS(on), ON−RESISTANCE (mW) ID, Drain Current (A) 30 VGS = 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V 5.5 V 2.5 2.0 1.5 1.0 0.5 0.0 40 VGS = 10 V ID = 6 A −50 0 50 100 150 TJ, Junction Temperature (5C) Figure 6. On−Resistance Variation vs. Temperature Figure 5. On−Resistance Variation vs. Drain Current and Gate Voltage www.onsemi.com 3 10 NVD260N65S3 TYPICAL CHARACTERISTICS 100000 1E−05 10000 TJ = 150°C Capacitances (pF) IDSS, Leakage Current (A) 1E−04 1E−06 TJ = 125°C 1E−07 TJ = 75°C 1E−08 100 1 50 350 450 550 150 250 VDS, Drain−to−Source Voltage (V) 0.1 0.1 650 Figure 7. Drain−to−Source Leakage Current vs. Voltage 100 ID = 6 A 8 VDS = 130 V VDS = 400 V 6 4 0 6 12 18 24 Qg, Total Gate Charge (nC) 1 10 100 VDS, Drain−Source Voltage (V) 1000 VGS = 0 V 250 ms Pulse Test 10 150°C 1 25°C 0.1 −55°C 0.001 0.0 30 Figure 9. Gate Charge Characteristics 1.2 BVDSS, Drain−Source Breakdown Voltage (Normalized) 10 ms 10 1 ms 100 ms 1 DC Operation in this Area is Limited by RDS(on) TC = 25°C TJ = 150°C Single Pulse 0.1 1 10 100 ms 10 ms 100 0.5 1.0 1.5 VSD, Body Diode Forward Voltage (V) Figure 10. Body Diode Forward Voltage Variation vs. Source Current and Temperature 100 ID, Drain Current (A) Crss 0.01 2 0.01 VGS = 0 V f = 1 MHz Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd Figure 8. Capacitance Characteristics IS, Reverse Drain Current (A) VGS, Gate−Source Voltage (V) 10 0 Coss 10 1E−09 1E−10 Ciss 1000 1.1 1.0 0.9 0.8 1000 VDS, Drain−Source Voltage (V) VGS = 0 V ID = 10 mA −50 50 100 150 0 TJ, Junction Temperature (5C) Figure 12. Breakdown Voltage Variation vs. Temperature Figure 11. Maximum Safe Operating Area www.onsemi.com 4 NVD260N65S3 TYPICAL CHARACTERISTICS 1.2 Normalized Gate Threshold Voltage EOSS, (mJ) 6 4 2 0 0 130 260 390 520 VDS, Drain to Source Voltage (V) 650 r(t), Normalized Effective Transient Thermal Resistance 1 0.1 1 0.8 0.6 −80 −40 40 80 120 160 Figure 14. Normalized Gate Threshold Voltage vs. Temperature DUTY CYCLE − DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 0.001 −5 10 0 TJ, AMBIENT TEMPERATURE (5C) Figure 13. EOSS vs. Drain to Source Voltage 2 ID = 290 mA SINGLE PULSE −4 10 t2 ZqJC(t) = r(t) x RqJC RqJC = 1.39°C/W Peak TJ = PDM x ZqJC(t) + TC Duty Cycle, D = t1 / t2 −3 −2 −1 10 10 10 t, Rectangular Pulse Duration (sec) Figure 15. Transient Thermal Response Curve www.onsemi.com 5 0 10 1 10 NVD260N65S3 VGS RL Qg VDS VGS Qgs Qgd DUT IG = Const. Charge Figure 16. Gate Charge Test Circuit & Waveform RL VDS VDS 90% 90% 90% VDD VGS RG VGS DUT VGS 10% td(on) 10% tr td(off) ton tf toff Figure 17. Resistive Switching Test Circuit & Waveforms L E AS + 1 @ LI AS 2 VDS BVDSS ID IAS RG VDD DUT VGS 2 ID(t) VDD VDS(t) tp tp Figure 18. Unclamped Inductive Switching Test Circuit & Waveforms www.onsemi.com 6 Time NVD260N65S3 + DUT VDS − ISD L Driver RG Same Type as DUT VGS − dv/dt controlled by RG − ISD controlled by pulse period D+ VGS (Driver) VDD Gate Pulse Width Gate Pulse Period 10 V IFM, Body Diode Forward Current ISD (DUT) di/dt IRM Body Diode Reverse Current Body Diode Recovery dv/dt VDS (DUT) VDD VSD Body Diode Forward Voltage Drop Figure 19. Peak Diode Recovery dv/dt Test Circuit & Waveforms SUPERFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 7 NVD260N65S3 PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F A E b3 c2 4 L3 Z D 1 L4 C A B 2 NOTE 7 c SIDE VIEW b TOP VIEW H DETAIL A 3 b2 e 0.005 (0.13) M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 8 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− NVD260N65S3 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 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