NTD4810N, NVD4810N
Power MOSFET
30 V, 54 A, Single N−Channel, DPAK/IPAK
Features
•
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
NVD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(on) MAX
ID MAX
10 mW @ 10 V
30 V
54 A
15.7 mW @ 4.5 V
Applications
D
• CPU Power Delivery
• DC−DC Converters
N−Channel
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
"20
V
ID
12.4
A
S
4
Continuous Drain
Current (RqJA) (Note 1)
TA = 25°C
Power Dissipation
(RqJA) (Note 1)
TA = 25°C
PD
2.62
W
Continuous Drain
Current (RqJA) (Note 2)
TA = 25°C
ID
9
A
3
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
Steady
State
9.6
TA = 85°C
7
TA = 25°C
PD
1.4
W
Continuous Drain
Current (RqJC)
(Note 1)
TC = 25°C
ID
54
A
Power Dissipation
(RqJC) (Note 1)
TC = 25°C
PD
50
W
TA = 25°C
IDM
120
A
TA = 25°C
IDmaxPkg
45
A
TJ, Tstg
−55 to
175
°C
IS
41
A
Drain to Source dV/dt
dV/dt
6.0
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 24 V, VGS = 10 V,
L = 1.0 mH, IL(pk) = 14 A, RG = 25 W)
EAS
98
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Pulsed Drain Current
TC = 85°C
tp=10ms
Current Limited by Package
Operating Junction and Storage Temperature
Source Current (Body Diode)
42
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2011
April, 2017 − Rev. 11
1
1 2
4
Drain
AYWW
48
10NG
Power Dissipation
(RqJA) (Note 2)
TA = 85°C
2
1 Drain 3
Gate Source
A
= Assembly Location*
Y
= Year
WW
= Work Week
4810N = Device Code
G
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Publication Order Number:
NTD4810N/D
NTD4810N, NVD4810N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction−to−Case (Drain)
Parameter
RqJC
3.0
°C/W
Junction−to−TAB (Drain)
RqJC−TAB
3.5
Junction−to−Ambient − Steady State (Note 1)
RqJA
57.2
Junction−to−Ambient − Steady State (Note 2)
RqJA
107.3
1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Parameter
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
27
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = "20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
"100
nA
2.5
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
VGS(TH)/TJ
RDS(on)
5.2
VGS = 10 to
11.5 V
ID = 30 A
8.0
ID = 15 A
7.8
VGS = 4.5 V
ID = 30 A
12
ID = 15 A
Forward Transconductance
gFS
1.5
VDS = 15 V, ID = 10 A
mV/°C
10
mW
15.7
11
9.0
S
CHARGES AND CAPACITANCES
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
1165
1350
284
330
Crss
154
200
Total Gate Charge
QG(TOT)
9.2
11
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
VGS = 0 V, f = 1.0 MHz,
VDS = 12 V
VGS = 4.5 V, VDS = 15 V,
ID = 30 A
pF
nC
1.3
3.3
4.4
VGS = 11.5 V, VDS = 15 V,
ID = 30 A
21
nC
11.5
ns
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(on)
tr
td(off)
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
20.7
13.8
tf
3.8
td(on)
7.2
tr
td(off)
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
20.7
21.8
2.6
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
ns
NTD4810N, NVD4810N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
TJ = 25°C
0.92
1.2
V
TJ = 125°C
0.79
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Time
VGS = 0 V,
IS = 30 A
18.2
VGS = 0 V, dIs/dt = 100 A/ms,
IS = 30 A
ns
10.6
7.6
QRR
8.8
nC
Source Inductance
LS
2.49
nH
Drain Inductance, DPAK
LD
0.0164
Drain Inductance, IPAK
LD
Gate Inductance
LG
3.46
Gate Resistance
RG
2.4
PACKAGE PARASITIC VALUES
TA = 25°C
1.88
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
NTD4810N, NVD4810N
TYPICAL PERFORMANCE CURVES
50
60
4V
10 V
6V
5V
4.5 V
VDS ≥ 10 V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
60
3.8 V
TJ = 25°C
40
3.6 V
30
3.4 V
20
3.2 V
3V
10
2.8 V
0
30
20
TJ = 125°C
TJ = 25°C
10
TJ = −55°C
1
4
3
2
0
5
1
2
3
4
5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.048
ID = 30 A
TJ = 25°C
0.043
0.038
0.033
0.028
0.023
0.018
0.013
0.008
0.003
3
4
6
5
7
8
9
10
0.020
TJ = 25°C
0.015
VGS = 4.5 V
0.010
VGS = 11.5 V
0.005
0
10
15
20
25
30
35
40
45
50
55
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100,000
2.0
VGS = 0 V
ID = 30 A
VGS = 10 V
TJ = 175°C
10,000
1.5
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
40
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
50
1.0
0.5
0
−50 −25
1000
TJ = 125°C
100
10
0
25
50
75
100
125
150
175
5
10
15
20
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Drain Voltage
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4
25
NTD4810N, NVD4810N
2000
VDS = 0 V VGS = 0 V
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
TYPICAL PERFORMANCE CURVES
TJ = 25°C
C, CAPACITANCE (pF)
Ciss
1500
Ciss
1000
Crss
500
Coss
0
10
Crss
5
0
VGS
5
10
15
20
25
VDS
12
9
8
7
6
5
3
2
ID = 30 A
0 V < VGS < 11.5 V
TJ = 25°C
1
0
0 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
Figure 7. Capacitance Variation
30
1000
IS, SOURCE CURRENT (AMPS)
VDD = 15 V
ID = 30 A
VGS = 11.5 V
100
td(off)
tr
10
td(on)
tf
1
10
RG, GATE RESISTANCE (OHMS)
VGS = 0 V
25
100
15
10
5
100 ms
1
1 ms
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
10 ms
VGS = 20 V
SINGLE PULSE
TC = 25°C
0.7
0.8
1.0
0.9
Figure 10. Diode Forward Voltage vs. Current
1000
10
0.6
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
100
TJ = 25°C
20
0
0.5
1
I D, DRAIN CURRENT (AMPS)
Q2
Q1
4
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
t, TIME (ns)
QT
11
10
110
100
ID = 14 A
90
80
70
60
50
40
30
20
10
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
175
NTD4810N, NVD4810N
TYPICAL PERFORMANCE CURVES
I D, DRAIN CURRENT (AMPS)
100
25°C
100°C
125°C
10
1
0.1
10
100
PULSE WIDTH (ms)
1
1000
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
Figure 13. Avalanche Characteristics
1.0
D = 0.5
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
SINGLE PULSE
0.01
1.0E-05
1.0E-04
t1
t2
DUTY CYCLE, D = t1/t2
1.0E-03
1.0E-02
t, TIME (ms)
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1.0E-01
1.0E+00
1.0E+01
Figure 14. Thermal Response
ORDERING INFORMATION
Package
Shipping†
NTD4810NT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NVD4810NT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NVD4810NT4G−VF01
DPAK
(Pb−Free)
2500 / Tape & Reel
Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA−01
ISSUE B
4
1 2
DATE 03 JUN 2010
3
SCALE 1:1
A
E
b3
c2
B
Z
D
1
L4
A
4
L3
2
b2
H
DETAIL A
3
c
b
0.005 (0.13)
e
M
H
C
L2
GAUGE
PLANE
C
L
L1
DETAIL A
A1
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
YWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
6.17
0.243
SCALE 3:1
SEATING
PLANE
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13126D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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