NTD4813NH, NVD4813NH
MOSFET – Power, Single,
N-Channel, DPAK/IPAK
30 V, 40 A
Features
•
•
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
Low RG
NVD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(ON) MAX
13 mW @ 10 V
30 V
D
N−Channel
• CPU Power Delivery
• DC−DC Converters
• High Side Switching
G
S
4
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Gate−to−Source Voltage
Symbol
Value
Unit
VDSS
30
V
3
DPAK
CASE 369AA
(Bent Lead)
STYLE 2
VGS
±20
V
ID
9.0
A
Continuous Drain
Current RqJA
(Note 1)
TA = 25°C
Power Dissipation
RqJA (Note 1)
TA = 25°C
PD
1.94
W
Continuous Drain
Current RqJA
(Note 2)
TA = 25°C
ID
7.6
A
TA = 85°C
7.0
TA = 85°C
PD
1.27
W
Continuous Drain
Current RqJC
(Note 1)
TC = 25°C
ID
40
A
Power Dissipation
RqJC (Note 1)
TC = 25°C
PD
35.3
W
TA = 25°C
IDM
90
A
TA = 25°C
IDmaxPkg
35
A
TJ,
TSTG
−55 to
+175
°C
IS
29
A
dV/dt
6
V/ns
TC = 85°C
tp=10ms
Current Limited by Package
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Drain to Source dV/dt
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
5.9
TA = 25°C
Pulsed Drain
Current
1 2
AYWW
48
13NHG
Parameter
Drain−to−Source Voltage
Power Dissipation
RqJA (Note 2)
40 A
25.9 mW @ 4.5 V
Applications
Steady
State
ID MAX
31
2
1 Drain 3
Gate Source
A
Y
WW
4813NH
G
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
May, 2019 − Rev. 4
1
Publication Order Number:
NTD4813NH/D
NTD4813NH, NVD4813NH
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol
Value
Unit
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 24 V, VGS = 10 V,
IL = 17.2 Apk, L = 0.3 mH, RG = 25 W)
EAS
44.4
mJ
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
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2
NTD4813NH, NVD4813NH
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Junction−to−Case (Drain)
Parameter
RqJC
4.25
Junction−to−TAB (Drain)
RqJC−TAB
3.5
Junction−to−Ambient – Steady State (Note 1)
RqJA
77.5
Junction−to−Ambient – Steady State (Note 2)
RqJA
118.5
Unit
°C/W
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
24.5
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25 °C
1
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
Forward Transconductance
1.5
5.4
VGS = 10 V to
11.5 V
ID = 30 A
10.9
ID = 15 A
10.7
VGS = 4.5 V
ID = 30 A
20.9
ID = 15 A
18.5
gFS
VDS = 15 V, ID = 10 A
mV/°C
13
25.9
6.7
mW
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
115
Total Gate Charge
QG(TOT)
7.1
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
940
VGS = 0 V, f = 1.0 MHz, VDS = 12 V
VGS = 4.5 V, VDS = 15 V; ID = 30 A
201
1.6
3.4
pF
10
nC
3.0
VGS = 11.5 V, VDS = 15 V;
ID = 30 A
18.2
nC
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
10
VGS = 4.5 V, VDS = 15 V, ID = 15 A,
RG = 3.0 W
tf
19.5
10.3
ns
2.9
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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3
NTD4813NH, NVD4813NH
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) (continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
5.1
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
16.1
ns
17.2
1.8
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.95
TJ = 125°C
0.9
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 30 A
1.2
V
15
VGS = 0 V, dIs/dt = 100 A/ms,
IS = 30 A
9.9
ns
5.1
QRR
7.0
nC
Source Inductance
LS
2.49
nH
Drain Inductance, DPAK
LD
0.0164
Drain Inductance, IPAK
LD
Gate Inductance
LG
3.46
Gate Resistance
RG
0.55
PACKAGE PARASITIC VALUES
TA = 25°C
1.88
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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4
NTD4813NH, NVD4813NH
TYPICAL PERFORMANCE CURVES
5V
6V
60
60
TJ = 25°C
4.5 V
50
4.2 V
40
4V
3.8 V
3.6 V
30
20
3.4 V
3.2 V
3V
10
0
2
8
6
4
10
40
30
20
TJ = 125°C
TJ = 25°C
10
TJ = −55°C
0
2
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.03
0.02
0.01
2
8
6
4
12
10
0.05
TJ = 25°C
0.04
0.03
VGS = 4.5 V
0.02
0.01
VGS = 11.5 V
0
10
15
20
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
10,000
1.2
1.0
30
35
40
45
50
55
60
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
VGS = 0 V
ID = 20 A
VGS = 10 V
1.4
25
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.6
6
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID = 30 A
TJ = 25°C
1.8
4
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.04
0
VDS ≥ 10 V
50
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (AMPS)
70
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
10 V
8V
ID, DRAIN CURRENT (AMPS)
80
TJ = 150°C
1000
TJ = 100°C
0.8
0.6
−50 −25
0
25
50
75
100
125
150
175
100
0
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Drain Voltage
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5
30
NTD4813NH, NVD4813NH
TYPICAL PERFORMANCE CURVES
Ciss
C, CAPACITANCE (pF)
1000
12
800
600
400
Coss
200
0
Crss
0
10
5
15
20
30
25
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
9
15
10
Q2
3
5
ID = 30 A
TJ = 25°C
0
0
2
4
6
8
10
12
14 16
QG, TOTAL GATE CHARGE (nC)
18
0
20
IS, SOURCE CURRENT (AMPS)
35
td(off)
10
tr
VDD = 15 V
ID = 30 A
VGS = 11.5 V
tf
1
10
RG, GATE RESISTANCE (OHMS)
VGS = 0 V
30
20
15
10
5
0
0.2
100
100 ms
1 ms
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
10
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
10 ms
1
0.6
0.8
1.2
1.0
Figure 10. Diode Forward Voltage vs. Current
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
0.4
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1000
10
TJ = 25°C
25
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
I D, DRAIN CURRENT (AMPS)
VGS
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
td(on)
t, TIME (ns)
VDS
Q1
100
0.1
20
QT
6
Figure 7. Capacitance Variation
1
25
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS = 0 V
TJ = 25°C
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
15
1200
50
45
ID = 17.2 A
40
35
30
25
20
15
10
5
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
150
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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6
175
NTD4813NH, NVD4813NH
TYPICAL PERFORMANCE CURVES
I D, DRAIN CURRENT (AMPS)
100
125°C
10
25°C
100°C
1
0.1
10
100
PULSE WIDTH (ms)
1
1000
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
Figure 13. Avalanche Characteristics
1.0
D = 0.5
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
SINGLE PULSE
0.01
1.0E-05
1.0E-04
t1
t2
DUTY CYCLE, D = t1/t2
1.0E-03
1.0E-02
t, TIME (ms)
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1.0E-01
1.0E+00
1.0E+01
Figure 14. Thermal Response
ORDERING INFORMATION
Package
Shipping†
NTD4813NHT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NVD4813NHT4G*
DPAK
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA−01
ISSUE B
4
1 2
DATE 03 JUN 2010
3
SCALE 1:1
A
E
b3
c2
B
Z
D
1
L4
A
4
L3
2
b2
H
DETAIL A
3
c
b
0.005 (0.13)
e
M
H
C
L2
GAUGE
PLANE
C
L
L1
DETAIL A
A1
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
YWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
6.17
0.243
SCALE 3:1
SEATING
PLANE
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13126D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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