NVD5117PLT4G

NVD5117PL MOSFET – Power, Single, P-Channel -60 V, 16 mW, -61 A Features • • • • • Low RDS(on) to Minimize Conduction Losses High Current Capability Avalanche Energy Specified AEC−Q101 Qualified These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com RDS(on) V(BR)DSS ID 16 mW @ −10 V −60 V −61 A 22 mW @ −4.5 V S MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RqJC (Note 1) Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1 & 2) Power Dissipation RqJA (Notes 1 & 2) Pulsed Drain Current TC = 25°C Steady State Symbol Value Unit VDSS −60 V VGS "20 V ID −61 A TC = 100°C TC = 25°C Steady State PD ID 4 W 118 PD W 4.1 −419 A TA = 25°C IDmaxpkg 60 A TJ, Tstg −55 to 175 °C IS −118 A EAS 240 mJ TL 260 °C Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, IL(pk) = 40 A, L = 0.3 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit Junction−to−Case − Steady State (Drain) RqJC 1.3 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 37 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2017 June, 2019 − Rev. 2 MARKING DIAGRAMS & PIN ASSIGNMENT 2.1 IDM Source Current (Body Diode) 3 DPAK CASE 369C STYLE 2 A −11 TA = 25°C, tp = 10 ms Operating Junction and Storage Temperature 1 2 −8 TA = 100°C Current Limited by Package (Note 3) D 59 TA = 100°C TA = 25°C P−Channel −43 TC = 100°C TA = 25°C G 1 4 Drain AYWW 51 17LG Parameter 2 1 Drain 3 Gate Source A = Assembly Location* Y = Year WW = Work Week 5117L = Device Code G = Pb−Free Package * The Assembly Location Code (A) is front side optional. In cases where the Assembly Location is stamped in the package bottom (molding ejecter pin), the front side assembly code may be blank. ORDERING INFORMATION Device Package Shipping† NVD5117PLT4G DPAK (Pb−Free) 2500 / Tape & Reel DPAK NVD5117PLT4G− (Pb−Free) VF01 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NVD5117PL/D NVD5117PL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min V(BR)DSS VGS = 0 V, ID = −250 mA −60 Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS VGS = 0 V, VDS = −60 V V TJ = 25°C −1.0 TJ = 125°C −100 mA IGSS VDS = 0 V, VGS = "20 V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = −250 mA −2.5 V Drain−to−Source On Resistance RDS(on) VGS = −10 V, ID = −29 A 12 16 mW VGS = −4.5 V, ID = −29 A 16 22 gFS VDS = −15 V, ID = −15 A 30 S Input Capacitance Ciss 4800 pF Output Capacitance Coss VGS = 0 V, f = 1.0 MHz, VDS = −25 V Reverse Transfer Capacitance Crss "100 nA ON CHARACTERISTICS (Note 4) Froward Transconductance −1.5 CHARGES AND CAPACITANCES Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Plateau Voltage VGP 480 320 VDS = −48 V, ID = −29 A VGS = −4.5 V 49 VGS = −10 V 85 nC 3 VGS = −4.5 V, VDS = −48 V, ID = −29 A 13 28 3.2 V 22 ns SWITCHING CHARACTERISTICS (Notes 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) VGS = −4.5 V, VDS = −48 V, ID = −29 A, RG = 2.5 W tf 195 50 132 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C −0.86 TJ = 125°C −0.74 tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = −29 A 36 VGS = 0 V, dls/dt = 100 A/ms, Is = −29 A QRR −1.0 V ns 19 17 44 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. www.onsemi.com 2 NVD5117PL TYPICAL CHARACTERISTICS −4.5 V −4 V 80 −3.8 V 60 −3.6 V 40 −3.4 V 20 −3.2 V −3 V 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −4.2 V 100 0 1 2 3 4 40 TJ = −55°C 2 3 4 5 6 Figure 2. Transfer Characteristics 0.055 0.045 0.035 0.025 0.015 4 5 6 7 8 9 10 0.024 TJ = 25°C 0.022 VGS = −4.5 V 0.020 0.018 0.016 0.014 VGS = −10 V 0.012 0.010 10 100000 −IDSS, LEAKAGE (nA) 1.20 1.00 40 50 60 70 80 90 100 110 120 VGS = 0 V VGS = −10 V ID = −29 A 1.40 30 Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.00 1.60 20 −ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage 1.80 TJ = 25°C TJ = 125°C 20 −VGS, GATE−TO−SOURCE VOLTAGE (V) −VGS, GATE−TO−SOURCE VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 60 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) ID = −29 A TJ = 25°C 3 80 0 5 VDS ≥ −10 V 100 Figure 1. On−Region Characteristics 0.065 0.005 120 TJ = 25°C RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −ID, DRAIN CURRENT (A) VGS = −10 V −ID, DRAIN CURRENT (A) 120 TJ = 150°C 10000 TJ = 125°C 1000 0.80 0.60 −50 −25 0 25 50 75 100 125 150 175 100 5 10 15 20 25 30 35 40 45 50 55 TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 60 NVD5117PL 6000 VGS = 0 V TJ = 25°C 5500 C, CAPACITANCE (pF) 5000 Ciss 4500 4000 3500 3000 2500 2000 1500 1000 500 0 Coss Crss 0 10 20 30 40 50 −VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS 60 Qgs 4 Qgd 2 0 VDS = −48 V ID = −29 A TJ = 25°C 0 10 20 30 40 50 60 70 80 Figure 7. Capacitance Variation Figure 8. Gate−to−Source vs. Total Charge tf td(on) 10.0 VDD = −48 V ID = −29 A VGS = −10 V 1 10 IS, SOURCE CURRENT (A) td(off) 100 90 VGS = 0 V TJ = 25°C 100 80 60 40 20 0 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 RG, GATE RESISTANCE (W) −VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1000 VGS = −10 V Single Pulse TC = 25°C 100 100 ms 1 ms 10 ms 10 dc RDS(on) Limit Thermal Limit Package Limit 0.1 1 1.2 250 10 ms EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ) t, TIME (ns) 6 Qg, TOTAL GATE CHARGE (nC) tr 1.0 −ID, DRAIN CURRENT (A) 8 120 100.0 0.1 QT −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1000.0 1 10 10 100 ID = −40 A 200 150 100 50 0 25 50 75 100 125 150 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature www.onsemi.com 4 175 NVD5117PL RqJC(t) (°C/W) EFFECTIVE TRANSIENT THERMAL RESISTANCE TYPICAL CHARACTERISTICS 10 1 0.1 Duty Cycle = 0.5 0.2 0.1 0.05 0.02 0.01 0.01 0.000001 Single Pulse 0.00001 0.0001 0.001 PULSE TIME (sec) Figure 13. Thermal Response www.onsemi.com 5 0.01 0.1 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 B c2 4 L3 Z D 1 L4 C A 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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