NVD5484NL
Power MOSFET
60 V, 17 mW, 54 A, Single N−Channel
Logic Level, DPAK
Features
•
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
High Current Capability
Avalanche Energy Specified
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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RDS(on)
V(BR)DSS
60 V
Gate−to−Source Voltage
Continuous Drain Current RqJC (Notes 1 & 3)
Power Dissipation RqJC
(Note 1)
Continuous Drain Current RqJA (Notes 1, 2 &
3)
Power Dissipation RqJA
(Notes 1 & 2)
Pulsed Drain Current
TC = 25°C
Steady
State
Value
Unit
VDSS
60
V
VGS
"20
V
ID
54
A
TC = 100°C
TC = 25°C
Steady
State
PD
ID
A
10.7
PD
W
3.9
2.0
TA = 25°C, tp = 10 ms
IDM
305
A
TA = 25°C
IDmaxpkg
60
A
TJ, Tstg
−55 to
+175
°C
IS
83
A
EAS
125
mJ
TL
260
°C
Operating Junction and Storage Temperature
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL(pk) = 50 A, L = 0.1 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
4
7.6
TA = 100°C
Current Limited by
Package (Note 3)
S
W
100
50
TA = 100°C
TA = 25°C
N−Channel
G
38
TC = 100°C
TA = 25°C
D
Symbol
Value
Unit
Junction−to−Case − Steady State (Drain)
RqJC
1.5
°C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
38
1. The entire application environment impacts the thermal resistance values
shown, they are not constants and are only valid for the particular conditions
noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
1 2
3
DPAK
CASE 369AA
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENT
4
Drain
AYWW
54
84NLG
Drain−to−Source Voltage
Symbol
54 A
23 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
ID
17 mW @ 10 V
2
1 Drain 3
Gate Source
A
= Assembly Location*
Y
= Year
WW
= Work Week
5484NL = Device Code
G
= Pb−Free Package
* The Assembly Location Code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package bottom (molding ejecter
pin), the front side assembly code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
May, 2017 − Rev. 2
1
Publication Order Number:
NVD5484NL/D
NVD5484NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
V(BR)DSS
VGS = 0 V, ID = 250 mA
60
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
VGS = 0 V,
VDS = 60 V
V
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = "20 V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250 mA
Drain−to−Source On Resistance
RDS(on)
mA
"100
nA
1.9
2.5
V
VGS = 10 V, ID = 25 A
13.5
17
mW
23
ON CHARACTERISTICS (Note 4)
1.5
VGS = 4.5 V, ID = 25 A
18
gFS
VDS = 15 V, ID = 20 A
41
S
Input Capacitance
Ciss
1410
pF
Output Capacitance
Coss
VGS = 0 V, f = 1.0 MHz,
VDS = 25 V
Forward Transconductance
CHARGES AND CAPACITANCES
Reverse Transfer Capacitance
Crss
Total Gate Charge
QG(TOT)
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Gate Resistance
315
135
VDS = 48 V,
ID = 23 A
VGS = 4.5 V
VGS = 10 V
nC
27
48
0.9
VGS = 10 V, VDS = 48 V,
ID = 23 A
RG
4.4
19
8.5
W
td(on)
18
ns
tr
160
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(off)
VGS = 4.5 V, VDS = 48 V,
ID = 23 A, RG = 10 W
100
tf
110
td(on)
7.8
tr
td(off)
VGS = 10 V, VDS = 48 V,
ID = 23 A, RG = 10 W
tf
45
152
113
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
VSD
VGS = 0 V,
IS = 25 A
TJ = 25°C
0.9
TJ = 125°C
0.8
tRR
ta
tb
64
VGS = 0 V, dIs/dt = 100 A/ms,
IS = 23 A
QRR
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2
V
ns
33
31
118
4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
5. Switching characteristics are independent of operating junction temperatures.
1.2
nC
NVD5484NL
TYPICAL CHARACTERISTICS
ID, DRAIN CURRENT (A)
TJ = 25°C
3.4 V
30
20
3.0 V
10
2.8 V
2.6 V
0
1
2
3
4
TJ = 125°C
20
TJ = 25°C
TJ = −55°C
10
2
3
4
5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 2. Transfer Characteristics
ID = 50 A
TJ = 25°C
0.03
0.02
3
30
Figure 1. On−Region Characteristics
0.04
0.01
40
0
5
4
5
6
7
8
9
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VDS ≥ 5 V
VGS = 3.8 V
40
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (Normalized)
50
7.5 V
4.5 V
10 V
0.025
VGS = 4.5 V
TJ = 25°C
0.020
VGS = 10 V
0.015
0.010
5
15
25
35
45
55
65
75
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100,000
2.5
VGS = 0 V
ID = 25 A
VGS = 10 V
10,000
2.0
IDSS, LEAKAGE (nA)
ID, DRAIN CURRENT (A)
50
TJ = 150°C
1000
1.5
1.0
0.5
−50 −25
0
25
50
75
100
125
150
100
10
175
TJ = 125°C
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
60
NVD5484NL
TYPICAL CHARACTERISTICS
3000
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
VGS = 0 V
TJ = 25°C
2500
Ciss
2000
1500
Coss
1000
500
0
Crss
0
10
20
40
30
50
60
8
6
4
Qgd
VDS = 48 V
ID = 23 A
TJ = 25°C
0
0
10
20
30
40
50
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
IS, SOURCE CURRENT (A)
30
VDD = 48 V
ID = 23 A
VGS = 4.5 V
tr
td(off)
tf
100
td(on)
1
10
20
15
10
5
0
100
VGS = 0 V
TJ = 25°C
25
0
0.25
0.50
0.75
1.00
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
ID, DRAIN CURRENT (A)
t, TIME (ns)
Qgs
2
1000
10
QT
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
10
3500
100
VGS = 10 V
Single Pulse
TC = 25°C
10 mS
1 mS
100 mS
10
dc
1
RDS(on) Limit
Thermal Limit
Package Limit
0.1
0.01
0.1
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
100
NVD5484NL
TYPICAL CHARACTERISTICS
10
qjc (°C/W)
1 50% Duty Cycle
20%
10%
0.1 5%
2%
1%
0.01
0.001
Single Pulse
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 12. Thermal Response
ORDERING INFORMATION
Package
Shipping†
NVD5484NLT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NVD5484NLT4G−VF01
DPAK
(Pb−Free)
2500 / Tape & Reel
Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA−01
ISSUE B
4
1 2
DATE 03 JUN 2010
3
SCALE 1:1
A
E
b3
c2
B
Z
D
1
L4
A
4
L3
2
b2
H
DETAIL A
3
c
b
0.005 (0.13)
e
M
H
C
L2
GAUGE
PLANE
C
L
L1
DETAIL A
A1
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
YWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
6.17
0.243
SCALE 3:1
SEATING
PLANE
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13126D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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