NTD5802N, NVD5802N
MOSFET – Power, Single,
N-Channel, DPAK
40 V, 101 A
Features
•
•
•
•
•
•
•
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Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
MSL 1/260°C
100% Avalanche Tested
NVD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
RDS(on)
ID
4.4 mW @ 10 V
101 A
7.8 mW @ 5.0 V
50 A
V(BR)DSS
40 V
D
N−Channel
G
Applications
• CPU Power Delivery
• DC−DC Converters
• Motor Driver
S
4
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
40
V
Gate−to−Source Voltage
VGS
±20
V
ID
101
A
Continuous Drain Current (RqJC) (Note 1)
TC = 25°C
Power Dissipation
(RqJC) (Note 1)
TC = 25°C
PD
93.75
W
TA = 25°C
ID
16.4
A
Continuous Drain Current (RqJA) (Note 1)
TC = 85°C
Steady
State
78
TA = 85°C
Power Dissipation
(RqJA) (Note 1)
PD
2.5
W
TA = 25°C
IDM
300
A
TA = 25°C
IDmaxPkg
45
A
TJ, Tstg
−55 to
175
°C
IS
50
A
Drain to Source dV/dt
dV/dt
6.0
V/ns
Single Pulse Drain−to−Source Avalanche Energy (VDD = 32 V, VGS = 10 V,
L = 0.3 mH, IL(pk) = 40 A, RG = 25 W)
EAS
240
mJ
TL
260
°C
tp=10ms
Current Limited by Package
Operating Junction and Storage Temperature
Source Current (Body Diode)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
3
CASE 369C
DPAK
(Bent Lead)
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENT
4
Drain
12.7
TA = 25°C
Pulsed Drain Current
1 2
AYWW
58
02NG
Parameter
2
1 Drain 3
Gate Source
A
Y
WW
5802N
G
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
May, 2019 − Rev. 8
1
Publication Order Number:
NTD5802N/D
NTD5802N, NVD5802N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction−to−Case (Drain)
Parameter
RqJC
1.6
°C/W
Junction−to−Ambient − Steady State (Note 1)
RqJA
60
Junction−to−Ambient − Steady State (Note 2)
RqJA
105
1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 10 mA
40
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Parameter
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
40
VGS = 0 V,
VDS = 40 V
mV/°C
TJ = 25°C
1.0
TJ = 150°C
50
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
3.5
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
gFS
1.5
−7.4
mV/°C
VGS = 10 V, ID = 50 A
3.6
4.4
mW
VGS = 5.0 V, ID = 50 A
6.5
7.8
VDS = 15 V, ID = 15 A
16.8
S
5300
pF
CHARGES AND CAPACITANCES
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
VGS = 0 V, f = 1.0 MHz,
VDS = 12 V
850
VGS = 0 V, f = 1.0 MHz,
VDS = 25 V
5025
550
580
Crss
400
Total Gate Charge
QG(TOT)
75
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
15
td(on)
14
tr
52
VGS = 10 V, VDS = 15 V,
ID = 50 A
pF
100
nC
6.0
18
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(off)
VGS = 10 V, VDS = 20 V,
ID = 50 A, RG = 2.0 W
tf
ns
39
8.5
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTD5802N, NVD5802N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
V
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
VSD
VGS = 0 V,
IS = 50 A
TJ = 25°C
0.9
1.2
VGS = 0 V,
IS = 20 A
TJ = 25°C
0.8
1.0
tRR
ta
tb
25
VGS = 0 V, dIs/dt = 100 A/ms,
IS = 50 A
QRR
ns
15
10
15
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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3
NTD5802N, NVD5802N
TYPICAL PERFORMANCE CHARACTERISTICS
10 V
180
VDS ≥ 10 V
VGS = 5 V
7V
160
ID, DRAIN CURRENT (A)
200
6V
140
ID, DRAIN CURRENT (A)
200
TJ = 25°C
4.5 V
120
100
4.2 V
80
60
4V
40
3.8 V
3.6 V
20
0
0
1
2
3
4
5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
150
100
50
0
6
TJ = 25°C
TJ = 100°C
TJ = −55°C
2
3
4
5
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 2. Transfer Characteristics
0.010
VGS = 10 V
0.008
TJ = 150°C
0.006
TJ = 25°C
0.004
TJ = −55°C
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
0.002
10
30
50
70
90
110 130
150
170 190
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 1. On−Region Characteristics
TJ = 25°C
VGS = 5 V
VGS = 10 V
30
50
70
90
110
130
150
170
190
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100000
VGS = 0 V
ID = 50 A
VGS = 10 V
IDSS, LEAKAGE (nA)
1.5
0.015
0.014
0.013
0.012
0.011
0.010
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
Figure 3. On−Resistance vs. Drain Current
1.7
1.6
6
1.4
1.3
1.2
1.1
1
TJ = 150°C
10000
1000
TJ = 100°C
0.9
0.8
0.7
−50
−25
0
25
50
75
100
125
150
100
175
2
6
10
14
18
22
26
30
34
38
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
NTD5802N, NVD5802N
VGS, GATE−TO−SOURCE VOLTAGE (V)
Ciss
7000
VGS = 0 V
TJ = 25°C
5000
4000
3000
2000
Coss
1000
Crss
0
ID = 50 A
TJ = 25°C
12
6000
C, CAPACITANCE (pF)
30
15
8000
10 5
0
5
10 15 20 25 30 35 40
VGS
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
9
6
6
3
0
0
20
40
0
80
60
Qg, TOTAL GATE CHARGE (nC)
60
VDD = 20 V
ID = 50 A
VGS = 10 V
IS, SOURCE CURRENT (A)
td(off)
tr
tf
td(on)
10
1
10
100
VGS = 0 V
TJ = 25°C
50
40
30
20
10
0
0.4
0.8
0.6
1.0
1.2
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
ID, DRAIN CURRENT (A)
t, TIME (ns)
12
QDS
QGS
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
100
1
18
VGS
VDS
Figure 7. Capacitance Variation
1000
24
QT
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TYPICAL PERFORMANCE CHARACTERISTICS
100
10 ms
100 ms
10
1 ms
VGS = 10 V
Single Pulse
1 TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
0.1
10 ms
dc
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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5
100
1.4
NTD5802N, NVD5802N
r(t), Effective Transient Thermal Resistance
(°C/W)
TYPICAL PERFORMANCE CHARACTERISTICS
10
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
Single Pulse
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t, PULSE TIME (s)
Figure 12. Thermal Response
ORDERING INFORMATION
Package
Shipping†
NTD5802NT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NVD5802NT4G*
DPAK
(Pb−Free)
2500 / Tape & Reel
Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
4
1 2
DATE 21 JUL 2015
3
SCALE 1:1
A
E
b3
C
A
B
c2
4
L3
Z
D
1
L4
2
3
NOTE 7
b2
e
c
SIDE VIEW
b
0.005 (0.13)
TOP VIEW
H
DETAIL A
M
BOTTOM VIEW
C
Z
H
L2
GAUGE
PLANE
C
L
L1
DETAIL A
Z
SEATING
PLANE
BOTTOM VIEW
A1
ALTERNATE
CONSTRUCTIONS
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 9:
STYLE 10:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. ANODE
3. RESISTOR ADJUST
3. CATHODE
4. CATHODE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
5.80
0.228
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.028 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.114 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.72
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.90 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
6.17
0.243
SCALE 3:1
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
XXXXXX
A
L
Y
WW
G
3.00
0.118
1.60
0.063
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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