NVD5890NLT4G-VF01

NVD5890NL Power MOSFET 40 V, 3.7 mW, 123 A, Single N−Channel DPAK Features • • • • • Low RDS(on) to Minimize Conduction Losses MSL 1 @ 260°C 100% Avalanche Tested AEC Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant http://onsemi.com V(BR)DSS RDS(ON) MAX ID MAX 3.7 mW @ 10 V 40 V 123 A 5.5 mW @ 4.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 40 V Gate−to−Source Voltage VGS "20 V ID 123 A Continuous Drain Current (RqJC) (Notes 1 & 3) TC = 25°C Power Dissipation (RqJC) (Note 1) TC = 25°C PD 107 W TA = 25°C ID 24 A Continuous Drain Current (RqJA) (Notes 1, 2, 3) TC = 85°C Steady State Pulsed Drain Current TA = 25°C 18.5 PD 4.0 W TA = 25°C IDM 400 A TA = 25°C IDmaxPkg 100 A TJ, Tstg −55 to 175 °C IS 100 A Single Pulse Drain−to−Source Avalanche Energy (VGS = 10 V, L = 0.3 mH, IL(pk) = 46.2 A, RG = 25 W) EAS 320 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C tp=10ms Current Limited by Package (Note 3) Operating Junction and Storage Temperature Source Current (Body Diode) N−Channel G 95 TA = 85°C Power Dissipation (RqJA) (Notes 1 & 2) D Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and suty cycle. S 4 1 2 3 CASE 369C DPAK (Bent Lead) STYLE 2 MARKING DIAGRAMS & PIN ASSIGNMENT 4 Drain YWW 58 90NLG Parameter 2 1 Drain 3 Gate Source Y = Year WW = Work Week 5890NL = Device Code G = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2012 October, 2012 − Rev. 0 1 Publication Order Number: NVD5890NL/D NVD5890NL THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction−to−Case (Drain) Parameter RqJC 1.4 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 37 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 40 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Parameter Typ Max Unit OFF CHARACTERISTICS V 40 Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = "20 V VGS(TH) VGS = VDS, ID = 250 mA VGS = 0 V, VDS = 40 V TJ = 25°C mV/°C 1.0 TJ = 150°C mA 100 "100 nA 2.5 V ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) Forward Transconductance gFS 1.5 7.4 mV/°C VGS = 10 V, ID = 50 A 2.9 3.7 mW VGS = 4.5 V, ID = 50 A 4.4 5.5 VDS = 15 V, ID = 15 A 16.3 S 4760 pF CHARGES AND CAPACITANCES Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss VGS = 0 V, f = 1.0 MHz, VDS = 25 V 580 VGS = 10 V, VDS = 15 V, ID = 50 A 84 nC 42 nC 385 Total Gate Charge QG(TOT) Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 18.8 td(on) 12 VGS = 4.5 V, VDS = 15 V, ID = 50 A 4.2 13.7 SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(off) VGS = 10 V, VDS = 20 V, ID = 50 A, RG = 2.0 W tf 35 38 11 4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns NVD5890NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit V DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 50 A TJ = 25°C 0.86 1.2 VGS = 0 V, IS = 20 A TJ = 25°C 0.78 1.0 tRR ta tb 35 VGS = 0 V, dIs/dt = 100 A/ms, IS = 50 A QRR 19 16 34 http://onsemi.com 3 ns nC NVD5890NL TYPICAL PERFORMANCE CURVES 250 VGS = 4.4 V 150 4V 100 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 200 3.6 V 50 0 250 TJ = 25°C 4.8 V 10 V 3.2 V 0.0 VDS ≥ 10 V 200 150 TJ = 125°C 100 TJ = 25°C 50 TJ = −55°C 1.0 2.0 3.0 4.0 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0 2.0 5.0 ID = 50 A TJ = 25°C 0.008 0.006 0.004 0.002 0.000 2 4 3 6 5 7 8 9 5.0 Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.010 10 0.010 TJ = 25°C 0.008 0.006 VGS = 4.5 V 0.004 VGS = 10 V 0.002 0.001 40 0 80 120 160 200 240 280 VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.0 100000 VGS = 0 V ID = 50 A VGS = 10 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics 2.5 3.0 3.5 4.0 4.5 VGS, GATE−TO−SOURCE VOLTAGE (V) 1.5 1.0 0.5 −50 −25 0 25 50 75 100 125 150 175 TJ = 150°C 10000 TJ = 125°C 1000 5 10 15 20 25 30 35 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Drain Voltage http://onsemi.com 4 40 NVD5890NL 7000 VGS = 0 V TJ = 25°C C, CAPACITANCE (pF) 6000 Ciss 5000 4000 3000 2000 Coss 1000 Crss 0 0 10 20 30 DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL PERFORMANCE CURVES 40 10 QT 8 6 Qgs 4 VDS = 15 V ID = 50 A TJ = 25°C 2 0 0 10 Figure 7. Capacitance Variation 20 30 40 50 60 70 QG, TOTAL GATE CHARGE (nC) 80 90 Figure 8. Gate−To−Source Voltage vs. Total Charge 100 VDD = 20 V ID = 50 A VGS = 10 V td(off) td(on) tr 100 tf 10 1 10 IS, SOURCE CURRENT (A) 1000 100 VGS = 0 V TJ = 25°C 75 50 25 0 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1000 I D, DRAIN CURRENT (AMPS) t, TIME (ns) Qgd 10 ms 100 100 ms 10 1 0.1 VGS ≤ 20 V SINGLE PULSE TC = 25°C 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 dc 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 5 100 NVD5890NL r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (°C/W) TYPICAL PERFORMANCE CURVES 10 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.001 0.000001 0.00001 RqJC = 1.4°C/W Steady State 0.0001 0.001 0.01 t, TIME (s) 0.1 1 10 100 1000 Figure 12. Thermal Response ORDERING INFORMATION Order Number NVD5890NLT4G Package Shipping† DPAK (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 C A B c2 4 L3 Z D 1 L4 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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