NVD5C632NLT4G

NVD5C632NL MOSFET – Power, Single N-Channel 60 V, 2.5 mW, 155 A Features • • • • Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com V(BR)DSS ID RDS(on) 2.5 mW @ 10 V 60 V 3.4 mW @ 4.5 V 155 A MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RqJC (Notes 1 & 3) Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1, 2 & 3) TC = 25°C Steady State Pulsed Drain Current Value Unit VDSS 60 V VGS "20 V ID 155 A TC = 100°C TC = 25°C 110 PD TC = 100°C TA = 25°C Power Dissipation RqJA (Notes 1 & 2) Symbol Steady State 58 ID TA = 100°C TA = 25°C Operating Junction and Storage Temperature Source Current (Body Diode) S N−CHANNEL MOSFET A 29 PD W 4 2 IDM 900 A TJ, Tstg −55 to 175 °C IS 96 A Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, IL(pk) = 14.4 A) EAS 363 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter G 4 21 TA = 100°C TA = 25°C, tp = 10 ms W 115 D Symbol Value Unit Junction−to−Case (Drain) (Note 1) RqJC 1.3 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 37 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. 1 2 3 DPAK CASE 369C STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain AYWW 5C 632LG Parameter 2 1 Drain 3 Gate Source A = Assembly Location Y = Year WW = Work Week 5C632L = Device Code G = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2015 June, 2019 − Rev. 1 1 Publication Order Number: NVD5C632NL/D NVD5C632NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 60 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Parameter Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS V 24 VGS = 0 V, VDS = 60 V mV/°C TJ = 25°C 10 TJ = 125°C 250 IGSS VDS = 0 V, VGS = 20 V VGS(TH) VGS = VDS, ID = 250 mA mA 100 nA 2.1 V ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance VGS(TH)/TJ RDS(on) 1.2 5.8 mV/°C mW VGS = 10 V, ID = 50 A 2.1 2.5 VGS = 4.5 V, ID = 50 A 2.7 3.4 VDS = 3 V, ID = 50 A 185 S 5700 pF gFS CHARGES, CAPACITANCES AND GATE RESISTANCES Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge QG(TOT) VGS = 0 V, f = 1.0 MHz, VDS = 25 V VDS = 48 V, ID = 50 A 2800 36 VGS = 4.5 V 34 VGS = 10 V 78 nC nC Total Gate Charge QG(TOT) 34.0 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Plateau Voltage VGP 3.1 V Gate Resistance RG 0.7 W td(on) 20 ns 9.5 VGS = 4.5 V, VDS = 48 V, ID = 50 A 16.8 6.1 SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(off) VGS = 4.5 V, VDS = 48 V, ID = 50 A, RG = 2.5 W tf 126 65 121 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD VGS = 0 V, IS = 50 A TJ = 25°C 0.8 TJ = 125°C 0.7 tRR 71 Charge Time ta 36 Discharge Time tb Reverse Recovery Charge VGS = 0 V, dIs/dt = 100 A/ms, IS = 50 A QRR www.onsemi.com 2 V ns 36 110 4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. 1.2 nC NVD5C632NL TYPICAL CHARACTERISTICS 10 V to 4.5 V 3.4 V 3.2 V 200 160 3.0 V 120 2.8 V 80 2.6 V 40 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) 0 160 0.5 1.5 1.0 2.0 80 0 2.5 TJ = 125°C 0 3 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 6 5 4 3 2 1 3 2 4 6 5 7 8 9 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 4 3.5 TJ = 25°C 3.0 VGS = 4.5 V 2.5 VGS = 10 V 2.0 1.5 10 20 30 40 50 60 80 70 90 100 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.0 100K VGS = 10 V ID = 50 A TJ = 150°C IDSS, LEAKAGE (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE TJ = −55°C 2 VGS, GATE−TO−SOURCE VOLTAGE (V) 7 1.8 1 VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ = 25°C ID = 50 A 1 TJ = 25°C 120 40 8 0 200 2.4 V 2.2 V 0 VDS = 3 V 240 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) ID, DRAIN CURRENT (A) 240 280 VGS = 3.6 V ID, DRAIN CURRENT (A) 280 1.6 10K 1.4 1.2 1.0 TJ = 125°C 1K TJ = 85°C 0.8 0.6 −50 −25 0 25 50 75 100 125 150 175 100 5 15 25 35 45 55 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 NVD5C632NL TYPICAL CHARACTERISTICS C, CAPACITANCE (pF) CISS COSS 1K 100 CRSS 10 1 VGS = 0 V TJ = 25°C f = 1 MHz 0 10 20 30 40 50 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 10K 60 QT 9 8 7 6 5 QGS 4 QGD 3 VDS = 48 V TJ = 25°C ID = 50 A 2 1 0 10 0 20 30 40 50 60 70 80 VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total Charge 100 1000 t, TIME (ns) td(off) IS, SOURCE CURRENT (A) VGS = 0 V tf tr 100 td(on) 10 VGS = 4.5 V VDS = 48 V ID = 50 A 1 10 0.3 0.4 TJ = −55°C TJ = 25°C 0.5 0.6 0.7 0.8 0.9 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 100 IPEAK, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) TJ = 125°C 1 100 1000 100 VGS ≤ 10 V Single Pulse TC = 25°C 10 1 0.1 10 10 ms RDS(on) Limit Thermal Limit Package Limit 0.1 1 10 0.5 ms 1 ms 10 ms 100 1000 TJ(initial) = 25°C 10 TJ(initial) = 100°C 1 1E−04 1E−03 1E−02 VDS, DRAIN−TO−SOURCE VOLTAGE(V) TIME IN AVALANCHE (s) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Drain Current vs. Time in Avalanche www.onsemi.com 4 NVD5C632NL RqJA(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (°C/W) TYPICAL CHARACTERISTICS 100 50% Duty Cycle 10 1 20% 10% 5% 2% 1% 0.1 0.01 0.001 Single Pulse 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE TIME (sec) Figure 13. Thermal Response ORDERING INFORMATION Order Number NVD5C632NLT4G Package Shipping† DPAK (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 B c2 4 L3 Z D 1 L4 C A 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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