NVD5C668NL
Power MOSFET
60 V, 8.9 mW, 49 A, Single N−Channel
Features
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Parameter
Unit
VDSS
60
V
Gate−to−Source Voltage
VGS
"20
V
ID
49
A
Power Dissipation RqJC
(Note 1)
Continuous Drain
Current RqJA
(Notes 1, 2 & 3)
TC = 25°C
Steady
State
TC = 100°C
TC = 25°C
Power Dissipation RqJA
(Notes 1 & 2)
Pulsed Drain Current
Steady
State
ID
W
44
PD
4
1.5
250
A
−55 to
175
°C
IS
25
A
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, IL(pk) = 3 A)
EAS
104
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
S
N−CHANNEL MOSFET
IDM
Source Current (Body Diode)
G
W
3.1
TJ, Tstg
TA = 25°C, tp = 10 ms
49 A
D
A
13
9.0
TA = 100°C
Operating Junction and Storage Temperature
12.8 mW @ 4.5 V
22
TA = 100°C
TA = 25°C
ID
8.9 mW @ 10 V
34
PD
TC = 100°C
TA = 25°C
RDS(on)
V(BR)DSS
60 V
Value
Drain−to−Source Voltage
Continuous Drain Current RqJC (Notes 1 & 3)
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Symbol
Value
Unit
°C/W
Junction−to−Case (Drain) (Note 1)
RqJC
3.4
Junction−to−Ambient − Steady State (Note 2)
RqJA
48.7
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
1 2
3
DPAK
CASE 369C
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
AYWW
5C
668LG
•
•
•
•
2
1 Drain 3
Gate Source
A
= Assembly Location
Y
= Year
WW
= Work Week
5C668L = Device Code
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
March, 2018 − Rev. 1
1
Publication Order Number:
NVD5C668NL/D
NVD5C668NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
60
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Parameter
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
27
VGS = 0 V,
VDS = 60 V
mV/°C
TJ = 25°C
10
TJ = 125°C
250
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 50 mA
mA
100
nA
2.1
V
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
VGS(TH)/TJ
RDS(on)
gFS
1.2
4.8
mV/°C
mW
VGS = 10 V, ID = 25 A
7.4
8.9
VGS = 4.5 V, ID = 25 A
10.2
12.8
VDS = 15 V, ID = 25 A
60
S
1300
pF
CHARGES, CAPACITANCES AND GATE RESISTANCES
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Threshold Gate Charge
QG(TOT)
VGS = 0 V, f = 1.0 MHz,
VDS = 25 V
VDS = 48 V,
ID = 25 A
580
18
VGS = 4.5 V
8.7
VGS = 10 V
18.7
QG(TH)
nC
nC
2.4
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Plateau Voltage
VGP
3.1
V
td(on)
12
ns
VGS = 4.5 V, VDS = 48 V,
ID = 25 A
4.1
2.0
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(off)
VGS = 4.5 V, VDS = 48 V,
ID = 25 A, RG = 2.5 W
tf
74
26
62
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
VGS = 0 V,
IS = 20 A
TJ = 25°C
0.87
TJ = 125°C
0.76
tRR
32
Charge Time
ta
15
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V, dIs/dt = 100 A/ms,
IS = 25 A
QRR
www.onsemi.com
2
V
ns
16
20
4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
5. Switching characteristics are independent of operating junction temperatures.
1.2
nC
NVD5C668NL
TYPICAL CHARACTERISTICS
VDS = 10 V
ID, DRAIN CURRENT (A)
80
3.6 V
60
3.4 V
3.2 V
40
3.0 V
20
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
100
VGS = 10 V to 5 V
2.8 V
2.6 V
0
0.5
1.0
1.5
2.0
2.5
40
TJ = 25°C
20
TJ = 125°C
0
3
4
Figure 2. Transfer Characteristics
25
20
15
10
5
4
5
6
7
8
9
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
5
14
12
VGS = 4.5 V
10
8
VGS = 10 V
6
4
2
TJ = 25°C
0
10
20
30
40
50
60
80
70
90
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.0
100K
IDSS, LEAKAGE (nA)
VGS = 10 V
ID = 25 A
1.6
1.4
1.2
1.0
TJ = 150°C
10K
TJ = 125°C
1K
TJ = 85°C
100
0.8
0.6
−50 −25
0
25
50
75
100
125
150
100
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
2
Figure 1. On−Region Characteristics
TJ = 25°C
ID = 25 A
1.8
1
TJ = −55°C
VGS, GATE−TO−SOURCE VOLTAGE (V)
30
3
60
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
35
0
80
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
ID, DRAIN CURRENT (A)
100
175
10
5
15
25
35
45
55
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NVD5C668NL
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
10K
CISS
1K
COSS
100
10
1
CRSS
VGS = 0 V
TJ = 25°C
f = 1 MHz
0
10
20
30
40
50
60
7
6
5
QGS
4
QGD
3
2
1
0
0
2
4
6
8
10
12
14
18
16
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source vs. Total Charge
100
IS, SOURCE CURRENT (A)
t, TIME (ns)
8
QG, TOTAL GATE CHARGE (nC)
VGS = 4.5 V
VDS = 48 V
ID = 25 A
tr
100
tf
td(off)
1
10
10
1
0.1
100
20
VGS = 0 V
TJ = 125°C
td(on)
0.3
0.4
0.5
TJ = 25°C
0.6
0.7
TJ = −55°C
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
100
10
10
1
0.1
0.1
VGS ≤ 10 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
1
TJ(initial) = 25°C
IPEAK, (A)
ID, DRAIN CURRENT (A)
VDS = 48 V
ID = 25 A
TJ = 25°C
9
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1000
10
10
10 ms
TJ(initial) = 100°C
1
0.5 ms
1 ms
10 ms
10
100
0.1
0.00001
1000
0.0001
0.001
0.01
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NVD5C668NL
TYPICAL CHARACTERISTICS
10
Duty Cycle = 50%
R(t) (°C/W)
1
20%
10%
5%
0.1 2%
1%
Single Pulse
0.01
0.001
1E−06
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
ORDERING INFORMATION
Order Number
NVD5C668NLT4G
Package
Shipping†
DPAK
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
4
1 2
DATE 21 JUL 2015
3
SCALE 1:1
A
E
b3
C
A
B
c2
4
L3
Z
D
1
L4
2
3
NOTE 7
b2
e
c
SIDE VIEW
b
0.005 (0.13)
TOP VIEW
H
DETAIL A
M
BOTTOM VIEW
C
Z
H
L2
GAUGE
PLANE
C
L
L1
DETAIL A
Z
SEATING
PLANE
BOTTOM VIEW
A1
ALTERNATE
CONSTRUCTIONS
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 9:
STYLE 10:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. ANODE
3. RESISTOR ADJUST
3. CATHODE
4. CATHODE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
5.80
0.228
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.028 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.114 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.72
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.90 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
6.17
0.243
SCALE 3:1
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
XXXXXX
A
L
Y
WW
G
3.00
0.118
1.60
0.063
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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