NTD6414AN, NVD6414AN
MOSFET – Power,
N-Channel
100 V, 32 A, 37 mW
Features
•
•
•
•
•
Low RDS(on)
High Current Capability
100% Avalanche Tested
NVD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
V(BR)DSS
RDS(on) MAX
ID MAX
(Note 1)
100 V
37 mW @ 10 V
32 A
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Gate−to−Source Voltage − Continuous
Continuous Drain
Current RqJC
Steady
State
Power Dissipation
RqJC
Steady
State
TC = 25°C
Value
Unit
VDSS
100
V
VGS
±20
V
ID
32
A
TC = 100°C
100
W
IDM
117
A
TJ, Tstg
−55 to
+175
°C
IS
32
A
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 50 Vdc, VGS = 10 Vdc,
IL(pk) = 32 A, L = 0.3 mH, RG = 25 W)
EAS
154
mJ
Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
TL
260
°C
tp = 10 ms
Operating and Storage Temperature Range
Source Current (Body Diode)
S
4
22
PD
Pulsed Drain Current
TC = 25°C
4
Symbol
Max
Unit
Junction−to−Case (Drain) Steady State
RqJC
1.5
°C/W
Junction−to−Ambient (Note 1)
RqJA
37
MARKING DIAGRAM
& PIN ASSIGNMENTS
4 Drain
2
Drain
A
Y
WW
6414AN
G
1. Surface mounted on FR4 board using 1 sq in pad size,
(Cu Area 1.127 sq in [1 oz] including traces).
2
3
IPAK
CASE 369D
STYLE 2
3
DPAK
CASE 369AA
STYLE 2
1
Gate
THERMAL RESISTANCE RATINGS
1
1 2
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Parameter
N−Channel
G
4 Drain
AYWW
64
14ANG
Drain−to−Source Voltage
Symbol
AYWW
64
14ANG
Parameter
3
Source
1
Gate
2
Drain
3
Source
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
May, 2019 − Rev. 2
1
Publication Order Number:
NTD6414AN/D
NTD6414AN, NVD6414AN
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
100
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Parameter
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
107
VGS = 0 V,
VDS = 100 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
100
IGSS
VDS = 0 V, VGS = "20 V
VGS(TH)
VGS = VDS, ID = 250 mA
"100
mA
nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
2.0
4.0
VGS(TH)/TJ
Drain−to−Source On−Resistance
RDS(on)
VGS = 10 V, ID = 32 A
30
gFS
VGS = 5.0 V, ID = 10 A
18
S
1450
pF
Forward Transconductance
8.3
V
Negative Threshold Temperature
Coefficient
mV/°C
37
mW
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
95
Total Gate Charge
QG(TOT)
40
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
VGS = 0 V, f = 1.0 MHz, VDS = 25 V
230
nC
1.7
VGS = 10 V, VDS = 80 V, ID = 32 A
8.0
QGD
20
Plateau Voltage
VGP
5.9
V
Gate Resistance
RG
1.9
W
td(on)
11
ns
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(off)
VGS = 10 V, VDD = 80 V,
ID = 32 A, RG = 6.1 W
tf
52
38
48
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
Ta
Discharge Time
Tb
Reverse Recovery Charge
VGS = 0 V, IS = 32 A
TJ = 25°C
0.87
TJ = 125°C
0.76
68
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 32 A
QRR
1.2
V
ns
51
16
195
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Surface mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
2
NTD6414AN, NVD6414AN
TYPICAL CHARACTERISTICS
60
ID, DRAIN CURRENT (A)
10 V
TJ = 25°C
70
7.5 V
6.5 V
50
6.0 V
40
30
5.5 V
20
5.0 V
10
2
3
4
30
20
5
2
3
5
6
7
Figure 2. Transfer Characteristics
0.05
0.04
0.03
5
6
7
8
9
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
VGS = 10 V
TJ = 175°C
0.08
TJ = 125°C
0.06
0.04
TJ = 25°C
0.02
TJ = −55°C
0.00
10
10000
IDSS, LEAKAGE (nA)
2
1.5
1
25
50
75
100
125
150
20
25
35
30
ID, DRAIN CURRENT (A)
VGS = 0 V
ID = 32 A
VGS = 10 V
0
15
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
3
−25
8
0.10
Figure 3. On−Region versus Gate Voltage
0.5
−50
4
Figure 1. On−Region Characteristics
0.06
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
TJ = −55°C
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 32 A
TJ = 25°C
2.5
TJ = 25°C
TJ = 125°C
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.07
0.02
40
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
1
50
10
4.5 V
0
0
VDS w 10 V
60
ID, DRAIN CURRENT (A)
70
TJ = 150°C
1000
10
175
TJ = 125°C
100
10
TJ, JUNCTION TEMPERATURE (°C)
20
30
40
50
60
70
80
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
90 100
Figure 6. Drain−to−Source Leakage Current
versus Voltage
http://onsemi.com
3
NTD6414AN, NVD6414AN
TJ = 25°C
VGS = 0 V
C, CAPACITANCE (pF)
2400
2000
1600
Ciss
1200
800
400
0
Coss
Crss
0
20
40
60
80
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
2800
100
VDS
4
40
2
0
20
ID = 32 A
TJ = 25°C
0
IS, SOURCE CURRENT (A)
t, TIME (ns)
tr
td(off)
td(on)
10
1
5
10
RG, GATE RESISTANCE (W)
35
0
40
25
20
15
10
5
0
0.4
100
0.5
0.6
0.7
0.8
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
0.9
Figure 10. Diode Forward Voltage versus
Current
100
160
AVALANCHE ENERGY (mJ)
10 ms
ID, DRAIN CURRENT (A)
10
15
20
25
30
Qg, TOTAL GATE CHARGE (nC)
TJ = 25°C
VGS = 0 V
30
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
100 ms
10
1 ms
VGS = 10 V
SINGLE PULSE
TC = 25°C
1
0.1
60
35
tf
1
Qgd
Figure 8. Gate−to−Source Voltage and
Drain−to−Source Voltage versus Total Charge
VDS = 80 V
ID = 32 A
VGS = 10 V
100
80
VGS
Qgs
6
Figure 7. Capacitance Variation
1000
100
QT
8
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1000
ID = 32 A
140
120
100
80
60
40
20
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE
175
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
http://onsemi.com
4
NTD6414AN, NVD6414AN
TYPICAL CHARACTERISTICS
10
R(t) (°C/W)
1 D = 0.5
0.2
0.1 0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
0.001
0.000001
0.00001
0.0001
0.001
0.01
t, PULSE TIME (s)
0.1
1
10
Figure 13. Thermal Response
ORDERING INFORMATION
Device
Package
Shipping†
NTD6414ANT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NTD6414AN−1G
IPAK
(Pb−Free)
75 Units / Rail
NVD6414ANT4G*
DPAK
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
*NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
http://onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
IPAK
CASE 369D−01
ISSUE C
SCALE 1:1
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
D
G
DATE 15 DEC 2010
H
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
T
MARKING
DIAGRAMS
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
Discrete
YWW
xxxxxxxx
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
xxxxxxxxx
A
lL
Y
WW
DOCUMENT NUMBER:
DESCRIPTION:
98AON10528D
Integrated
Circuits
xxxxx
ALYWW
x
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
IPAK (DPAK INSERTION MOUNT)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA−01
ISSUE B
4
1 2
DATE 03 JUN 2010
3
SCALE 1:1
A
E
b3
c2
B
Z
D
1
L4
A
4
L3
2
b2
H
DETAIL A
3
c
b
0.005 (0.13)
e
M
H
C
L2
GAUGE
PLANE
C
L
L1
DETAIL A
A1
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
YWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
6.17
0.243
SCALE 3:1
SEATING
PLANE
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13126D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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