NVGS3130NT1G

NTGS3130N, NVGS3130N MOSFET – Single, N-Channel, TSOP-6 20 V, 5.6 A, 24 mW Features • • • • • Leading Edge Trench Technology for Low On Resistance Low Gate Charge for Fast Switching Small Size (3 x 2.75 mm) TSOP−6 Package NV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable This is a Pb−Free Device http://onsemi.com V(BR)DSS 20 V RDS(on) mAX ID Max 24 mW @ 4.5 V 5.6 A 32 mW @ 2.5 V 4.9 A N−Channel Applications Drain 1 2 5 6 • DC−DC Converters • Lithium Ion Battery Applications • Load/Power Switching MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Gate 3 Symbol Value Unit Drain−to−Source Voltage VDSS 20 V Gate−to−Source Voltage VGS ±8 V Continuous Drain Current (Note 1) Power Dissipation (Note 1) Continuous Drain Current (Note 2) Power Dissipation (Note 2) Steady State TA = 25°C t ≤ 10 s TA = 25°C Steady State TA = 85°C TA = 25°C 5.6 ID 4.1 PD Drain Drain Source 6 5 4 1.1 W 1.4 TA = 25°C TA = 85°C ID 4.2 A 3.0 PD 0.6 W IDM 19 A TJ, Tstg −55 to 150 °C Source Current (Body Diode) IS 1.0 A Lead Temperature for Soldering Purposes (1/8” from case for 10 s) TL 260 °C Pulsed Drain Current TA = 25°C tP ≤ 10 s Operating and Storage Temperature Range THERMAL RESISTANCE RATINGS Parameter Junction−to−Ambient − Steady State (Note 2) 1 TSOP−6 CASE 318G STYLE 1 XX M G XX M G G 1 2 3 Drain Drain Gate = Specific Device Code = Date Code* = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation may vary depending upon manufacturing location. ORDERING INFORMATION Symbol Junction−to−Ambient − Steady State (Note 1) Junction−to−Ambient − t ≤ 10 s (Note 1) MARKING DIAGRAM & PIN ASSIGNMENT A 6.2 t ≤ 10 s Steady State Source 4 Max Unit 110 RqJA 90 See detailed ordering and shipping information ion page 5 of this data sheet. °C/W 200 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces) 2. Surface−mounted on FR4 board using the minimum recommended pad size © Semiconductor Components Industries, LLC, 2014 May, 2019 − Rev. 1 1 Publication Order Number: NTGS3130N/D NTGS3130N, NVGS3130N ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V; ID = 250 mA 20 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Characteristic Typ Max Unit OFF CHARACTERISTICS V 9.8 mV/°C Zero Gate Voltage Drain Current IDSS VGS = 0 V; VDS = 16 V, TJ = 25°C 1.0 mA Gate−to−Source Leakage Current IGSS VDS = 0, VGS = ± 8 V 100 nA VGS(TH) VGS = VDS, ID = 250 mA 1.4 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Temperature Coefficient VGS(TH)/TJ Drain−to−Source On−Resistance RDS(on) Forward Transconductance 0.4 0.6 3.4 gFS mV/°C VGS = 4.5 V, ID = 5.6 A 19 24 VGS = 2.5 V, ID = 4.9 A 25 32 VDS = 10 V, ID = 5.6 A 8.2 mW S CHARGES, CAPACITANCE, & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance VGS = 0 V, f = 1 MHz, VDS = 16 V VGS = 0 V, f = 1 MHz, VDS = 10 V CRSS 935 169 104 198 110 Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 4.2 Total Gate Charge QG(TOT) 11.8 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 13.2 VGS = 4.5 V VDS = 16 V ID = 5.6 A VGS = 4.5 V VDS = 5.0 V ID = 6.2 A pF 965 20.3 0.60 1.5 18.0 nC 0.6 1.4 2.7 SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) VGS = 4.5 V, VDD = 16 V, ID = 1 A, RG = 3 W tr td(OFF) tf 6.3 12.6 7.3 13.5 21.7 35.1 9.7 17.6 0.7 1.2 ns DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 1.0 A TJ = 25°C V 20.4 VGS = 0 Vdc, dISD/dt = 100 A/ms, IS = 1.0 A QRR 8.1 ns 11.6 8.8 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 NTGS3130N, NVGS3130N TYPICAL CHARACTERISTICS ID, DRAIN CURRENT (A) 1.8 V 2.0 V 16 12 8 1.5 V 4 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 25 VGS = 4.5 V to 2.5 V TJ = 25°C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 10 TJ = 25°C 5 TJ = −55°C 0.75 1.0 1.25 1.5 1.75 2.0 Figure 2. Transfer Characteristics 0.06 TJ = 125°C 0.04 TJ = 25°C 1.5 2 2.5 3 3.5 4 4.5 5 VGS, GATE VOLTAGE (V) 2.25 0.10 TJ = 25°C 0.08 VGS = 1.8 V 0.06 VGS = 2 V 0.04 VGS = 2.5 V 0.02 VGS = 4.5 V 3V 0.00 2 4 6 8 10 12 14 16 18 20 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 0.04 1400 1200 0.03 C, CAPACITANCE (pF) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) TJ = 125°C Figure 1. On−Region Characteristics 0.08 1 15 VGS, GATE−TO−SOURCE VOLTAGE (V) ID = 5.6 A 0 20 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.10 0.02 VDS ≥ 5 V 0 0.5 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (A) 20 VGS = 2.5 V 0.02 VGS = 4.5 V VGS = 0 V TJ = 25°C f = 1 MHz Ciss 1000 800 600 400 Coss 200 0.01 −50 −25 0 25 50 75 100 125 0 150 Crss 0 2 4 6 8 10 12 14 16 TJ, JUNCTION TEMPERATURE (°C) DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Capacitance Variation http://onsemi.com 3 18 20 NTGS3130N, NVGS3130N TYPICAL CHARACTERISTICS 6 VDS 14 VGS 4 12 VDS = 5 V 10 3 QGS QGD 8 VDS = 16 V 2 6 4 1 ID = 5.6 A TJ = 25°C 0 0 2 4 6 8 10 12 2 14 0 IS, SOURCE CURRENT (A) 5 16 V DS , DRAIN-TO-SOURCE VOLTAGE (V) V GS, GATE-TO-SOURCE VOLTAGE (V) 10 18 QT 125°C 25°C 1.0 TJ = −55°C 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 QG, TOTAL GATE CHARGE (nC) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 7. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge Figure 8. Diode Forward Voltage vs. Current 100 5 100 ms 1 ms 1 0.1 0.01 SINGLE PULSE RqJA = 110°C/W TA = 25°C 4 10 POWER (W) ID, DRAIN CURRENT (A) VGS = 0 V 10 ms VGS = 8 V SINGLE PULSE TC = 25°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 2 1 dc 10 1 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.1 3 0 100 0 10 1000 100 SINGLE PULSE TIME (s) Figure 9. Maximum Rated Forward Biased Safe Operating Area RqJA, EFFECTIVE TRANSIENT THERMAL RESISTANCE NORMALIZED 1 Figure 10. Single Pulse Maximum Power Dissipation 1 D = 0.5 0.1 0.2 0.1 0.05 0.02 0.01 0.01 0.001 0.000001 SINGLE PULSE 0.00001 0.0001 0.001 0.01 t, TIME (s) 0.1 Figure 11. Thermal Response http://onsemi.com 4 1 10 100 1000 NTGS3130N, NVGS3130N Table 1. ORDERING INFORMATION Part Number Marking (XX) Package Shipping† NTGS3130NT1G S9 TSOP−6 (Pb−Free) 3000 / Tape & Reel NVGS3130NT1G VS9 TSOP−6 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V 1 SCALE 2:1 D H ÉÉ ÉÉ 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b SEATING PLANE C DETAIL Z e DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)− 4. D(IN)− 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB14888C TSOP−6 1 IC 0.95 XXX MG G = Specific Device Code =Assembly Location = Year = Work Week = Pb−Free Package STANDARD XXX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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