NVHL040N65S3F
MOSFET – Power,
N-Channel, SUPERFET) III,
FRFET)
650 V, 65 A, 40 mW
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Description
SUPERFET III MOSFET is ON Semiconductor’s brand−new high
voltage super−junction (SJ) MOSFET family that is utilizing charge
balance technology for outstanding low on−resistance and lower gate
charge performance. This advanced technology is tailored to minimize
conduction loss, provide superior switching performance, and
withstand extreme dv/dt rate.
Consequently, SUPERFET III MOSFET is very suitable for the
various power system for miniaturization and higher efficiency.
SUPERFET III FRFET MOSFET’s optimized reverse recovery
performance of body diode can remove additional component and
improve system reliability.
VDSS
RDS(ON) MAX
ID MAX
650 V
40 mW @ 10 V
65 A
D
G
Features
•
•
•
•
•
•
700 V @ TJ = 150°C
Typ. RDS(on) = 33.8 mW
Ultra Low Gate Charge (Typ. Qg = 153 nC)
Low Effective Output Capacitance (Typ. Coss(eff.) = 1333 pF)
100% Avalanche Tested
AEC−Q101 Qualified and PPAP Capable
S
POWER MOSFET
Applications
G
• Automotive On Board Charger HEV−EV
• Automotive DC/DC converter for HEV−EV
S
TO−247 LONG LEADS
CASE 340CX
D
MARKING DIAGRAM
$Y&Z&3&K
NVHL
040N65S3F
$Y
&Z
&3
&K
NVHL040N65S3F
= ON Semiconductor Logo
= Assembly Plant Code
= Data Code (Year & Week)
= Lot
= Specific Device Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
July, 2019 − Rev. 1
1
Publication Order Number:
NVHL040N65S3F/D
NVHL040N65S3F
ABSOLUTE MAXIMUM RATINGS (TC = 25°C, Unless otherwise noted)
Symbol
Parameter
VDSS
Drain to Source Voltage
VGSS
Gate to Source Voltage
ID
Drain Current
NVHL040N65S3F
Unit
650
V
− DC
±30
V
− AC (f > 1 Hz)
±30
− Continuous (TC = 25°C)
65
− Continuous (TC = 100°C)
45
IDM
Drain Current
162.5
A
EAS
Single Pulsed Avalanche Energy (Note 2)
1009
mJ
EAR
Repetitive Avalanche Energy (Note 1)
4.46
mJ
dv/dt
MOSFET dv/dt
100
V/ns
Peak Diode Recovery dv/dt (Note 3)
50
PD
− Pulsed (Note 1)
A
Power Dissipation
(TC = 25°C)
− Derate Above 25°C
TJ, TSTG
TL
Operating and Storage Temperature Range
446
W
3.57
W/°C
−55 to +150
°C
300
°C
Maximum Lead Temperature for Soldering, 1/8″ from Case for 5 seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Repetitive rating: pulse−width limited by maximum junction temperature.
2. IAS = 9 A, RG = 25 W, starting TJ = 25°C.
3. ISD ≤ 32.5 A, di/dt ≤ 200 A/ms, VDD ≤ 400 V, starting TJ = 25°C.
THERMAL CHARACTERISTICS
Symbol
Parameter
RqJC
Thermal Resistance, Junction to Case, Max.
RqJA
Thermal Resistance, Junction to Ambient, Max.
NVHL040N65S3F
Unit
0.28
_C/W
40
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
Top Marking
Package
Packing Method
Reel Size
Tape Width
Quantity
NVHL040N65S3F
NVHL040N65S3F
TO−247
Tube
N/A
N/A
30 Units
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2
NVHL040N65S3F
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VGS = 0 V, ID = 1 mA, TJ = 25_C
650
−
−
V
VGS = 0 V, ID = 10 mA, TJ = 150_C
700
−
−
V
OFF CHARACTERISTICS
BVDSS
Drain to Source Breakdown Voltage
DBVDSS / DTJ
Breakdown Voltage Temperature
Coefficient
ID = 10 mA, Referenced to 25_C
−
0.64
−
V/_C
IDSS
Zero Gate Voltage Drain Current
VDS = 650 V, VGS = 0 V
−
−
10
mA
VDS = 520 V, TC = 125_C
−
103
−
IGSS
Gate to Body Leakage Current
VGS = ±30 V, VDS = 0 V
−
−
±100
nA
ON CHARACTERISTICS
VGS(th)
Gate Threshold Voltage
VGS = VDS, ID = 2.1 mA
3.0
−
5.0
V
RDS(on)
Static Drain to Source On Resistance
VGS = 10 V, ID = 32.5 A
−
33.8
40
mW
Forward Transconductance
VDS = 20 V, ID = 32.5 A
−
40
−
S
VDS = 400 V, VGS = 0 V, f = 1 MHz
−
5875
−
pF
−
140
−
pF
gFS
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Coss(eff.)
Effective Output Capacitance
VDS = 0 V to 400 V, VGS = 0 V
−
1333
−
pF
Coss(er.)
Energy Related Output Capacitance
VDS = 0 V to 400 V, VGS = 0 V
−
241
−
pF
Total Gate Charge at 10 V
VDS = 400 V, ID = 32.5 A, VGS = 10 V
(Note 4)
−
153
−
nC
−
51
−
nC
Qg(tot)
Qgs
Gate to Source Gate Charge
Qgd
Gate to Drain “Miller” Charge
ESR
Equivalent Series Resistance
−
61
−
nC
f = 1 MHz
−
1.9
−
W
VDD = 400 V, ID = 32.5 A, VGS = 10 V
Rg = 2.2 W
(Note 4)
−
41
−
ns
−
53
−
ns
SWITCHING CHARACTERISTICS
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
−
96
−
ns
Turn-Off Fall Time
−
28
−
ns
Maximum Continuous Source to Drain Diode Forward Current
−
−
65
A
ISM
Maximum Pulsed Source to Drain Diode Forward Current
−
−
162.5
A
VSD
Source to Drain Diode Forward Voltage
VGS = 0 V, ISD = 32.5 A
−
−
1.3
V
trr
Reverse Recovery Time
−
159
−
ns
Qrr
Reverse Recovery Charge
VGS = 0 V, ISD = 32.5 A,
dIF/dt = 100 A/ms
−
840
−
nC
tf
SOURCE-DRAIN DIODE CHARACTERISTICS
IS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Essentially independent of operating temperature typical characteristics.
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3
NVHL040N65S3F
TYPICAL CHARACTERISTICS
10
5.5 V
1
200
1
10
Figure 2. On−Region Characteristics
4
5
6
7
8
9
0.06
TC = 25°C
0.05
VGS = 10 V
0.04
VGS = 20 V
0.03
0.02
0
CAPACITANCE (pF)
IS, REVERSE DRAIN CURRENT (A)
TJ = 25°C
0.01
TJ = −55°C
0.5
150
180
Ciss
10K
1K
f = 1 MHz
VGS = 0 V
100
1.0
1.5
1
2.0
Coss
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
10
0
120
100K
1
0.001
90
1M
TJ = 150°C
0.1
60
Figure 4. On−Resistance Variation vs. Drain
Current and Gate Voltage
250 ms Pulse Test
VGS = 0 V
10
30
ID, DRAIN CURRENT (A)
Figure 3. Transfer Characteristics
100
20
10
Figure 1. On−Region Characteristics
VGS, GATE−TO−SOURCE VOLTAGE (V)
1000
1
VDS, DRAIN−SOURCE VOLTAGE (V)
TJ = −55°C
3
0.1
VDS, DRAIN−SOURCE VOLTAGE (V)
TJ = 150°C
1
5.5 V
10
1
TJ = 25°C
10
7.0 V
6.0 V
20
250 ms Pulse Test
VDS = 20 V
100
VGS = 10 V
8.0 V
6.5 V
250 ms Pulse Test
TC = 25°C
0.2
250 ms Pulse Test
TC = 150°C
100
RDS(ON), DRAIN−SOURCE ON−RESISTANCE (W)
ID, DRAIN CURRENT (A)
7.0 V
6.5 V
6.0 V
0.1
ID, DRAIN CURRENT (A)
200
8.0 V
VGS = 10 V
ID, DRAIN CURRENT (A)
200
100
10−1
100
101
Crss
102
VSD, BODY DIODE FORWARD VOLTAGE (V)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. Body Diode Forward Voltage
Variation vs. Source Current and Temperature
Figure 6. Capacitance Characteristics
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4
103
NVHL040N65S3F
VDD = 130 V
ID = 32.5 A
VDD = 400 V
8
6
4
2
0
0
60
120
180
1.2
VGS = 0 V
ID = 10 mA
1.1
1.0
0.9
0.8
−75
25
75
125
175
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Gate Charge Characteristics
Figure 8. Breakdown Voltage Variation vs.
Temperature
300
3.0
VGS = 10 V
ID = 32.5 A
2.0
1.5
1.0
0.5
0
−75
−25
25
75
125
10 ms
Operation in this Area
is Limited by RDS(ON)
DC
1
0.1
175
100 ms
1 ms
10
TC = 25°C
TJ = 150°C
Single Pulse
1
10
100
1K
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−SOURCE VOLTAGE (V)
Figure 9. On−Resistance Variation vs.
Temperature
Figure 10. Maximum Safe Operating Area
80
40
70
35
60
30
50
25
40
30
20
15
20
10
10
5
25
30 ms
100
ID, DRAIN CURRENT (A)
2.5
0
−25
Qg, TOTAL GATE CHARGECHARGE (nC)
Eoss (mJ)
ID, DRAIN CURRENT (A)
RDS(ON), DRAIN−SOURCE ON−RESISTANCE (Normalized)
VGS, GATE−SOURCE VOLTAGE (V)
10
BVDSS, DRAIN−SOURCE
BREAKDOWN VOLTAGE (Normalized)
TYPICAL CHARACTERISTICS
50
75
100
125
0
150
0
130
260
390
520
650
TC, CASE TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Drain Current vs. Case
Temperature
Figure 12. EOSS vs. Drain−to−Source Voltage
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NVHL040N65S3F
TYPICAL CHARACTERISTICS
POWER DISSIPATION MULTIPLIER
1.2
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
TC, CASE TEMPERATURE (°C)
Figure 13. Normalized Power Dissipation vs.
Case Temperature
IDM, PEAK CURRENT (A)
5000
VGS = 10 V
TC = 25°C
For temperatures above 25°C
derate peak current as follows:
1000
I + I 25
ƪǸ
150 * T C
125
ƫ
100
Single Pulse
10
10−5
10−4
10−3
10−2
10−1
100
t, RECTANGULAR PULSE DURATION (s)
Figure 14. Peak Current Capability
IAS, AVALANCHE CURRENT (A)
100
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS − VDD)
If R ≠ 0
tAV = (L/R)In[(IAS*R)/(1.3*RATED BVDSS − VDD) +1]
Starting TJ = 25°C
10
Starting TJ = 125°C
1
NOTE: Refer to Application
Notes AN7514 and AN7515
0.001
0.01
0.1
1
10
100
tAV, TIME IN AVALANCHE (ms)
Figure 15. Unclamped Inductive Switching
Capability
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6
101
NVHL040N65S3F
1.2
200
NRMALIZED GATE THRESHOLD
VOLTAGE
180
160
140
120
100
TA = 150°C
80
60
Pulse Duration = 250 ms
Duty Cycle = 0.5% Max
ID = 32.5 A
40
20
0
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
RDS(ON), DRAIN−SOURCE ON−RESISTANCE (mW)
TYPICAL CHARACTERISTICS
4
5
6
TA = 25°C
7
8
9
VGS = VDS
ID = 2.1 mA
1.0
0.8
0.6
−80
10
−40
0
40
80
120
160
VGS, GATE−TO−SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 16. RDS(ON) vs. Gate Voltage
Figure 17. Normalized Gate Threshold Voltage
vs. Temperature
10
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
PDM
0.01 0.01
0.001
t1
Single Pulse
0.00001
0.0001
0.001
t2
0.01
t, RECTANGULAR PULSE DURATION (s)
Figure 18. Transient Thermal Response Curve
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7
ZqJC(t) = r(t) x RqJC
RqJC = 0.28°C/W
Peak TJ = PDM x ZqJC(t) + TC
Duty Cycle, D = t1 / t2
0.1
1
NVHL040N65S3F
VGS
RL
Qg
VDS
VGS
Qgs
Qgd
DUT
IG = Const.
Charge
Figure 19. Gate Charge Test Circuit & Waveform
RL
VDS
VDS
90%
90%
90%
VDD
VGS
RG
VGS
DUT
VGS
10%
td(on)
10%
tr
td(off)
ton
tf
toff
Figure 20. Resistive Switching Test Circuit & Waveforms
L
E AS + 1 @ LI AS
2
VDS
BVDSS
ID
IAS
RG
VDD
DUT
VGS
2
ID(t)
VDD
VDS(t)
tp
tp
Figure 21. Unclamped Inductive Switching Test Circuit & Waveforms
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8
Time
NVHL040N65S3F
+
DUT
VDS
−
ISD
L
Driver
RG
Same Type
as DUT
VGS
− dv/dt controlled by RG
− ISD controlled by pulse period
D+
VGS
(Driver)
VDD
Gate Pulse Width
Gate Pulse Period
10 V
IFM, Body Diode Forward Current
ISD
(DUT)
di/dt
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
VDS
(DUT)
VDD
VSD
Body Diode
Forward Voltage Drop
Figure 22. Peak Diode Recovery dv/dt Test Circuit & Waveforms
SUPERFET and FRFET are a registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United
States and/or other countries.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247−3LD
CASE 340CX
ISSUE A
DATE 06 JUL 2020
GENERIC
MARKING DIAGRAM*
XXXXXXXXX
AYWWG
DOCUMENT NUMBER:
DESCRIPTION:
XXXXX
A
Y
WW
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”, may
or may not be present. Some products may
not follow the Generic Marking.
98AON93302G
TO−247−3LD
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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