NVLUS4C12N
MOSFET – Power, Single
N-Channel, mCool,
2.0x2.0x0.55 mm UDFN6
30 V, 10.7 A
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Features
• Low Profile UDFN 2.0 x 2.0 x 0.55 mm for Board Space Saving with
•
•
•
•
•
Exposed Drain Pads for Excellent Thermal Conduction
Ultra Low RDS(on) to Reduce Conduction Losses
Optimized Gate Charge to Reduce Switching Losses
Low Capacitance to Minimize Driver Losses
NV Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MOSFET
RDS(on) MAX
V(BR)DSS
ID MAX
9 mW @ 10 V
12 mW @ 4.5 V
30 V
10.7 A
15 mW @ 3.7 V
19 mW @ 3.3 V
D
Applications
G
• Power Load Switch
• Synch DC−DC Converters
• Wireless Charging Circuit
S
N−CHANNEL MOSFET
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol
Value
Unit
Drain-to-Source Voltage
VDSS
30
V
Gate-to-Source Voltage
VGS
±20
V
ID
10.7
A
Continuous Drain
Current (Note 1)
Power Dissipation (Note 1)
Continuous Drain
Current (Note 2)
Steady
State
TA = 25°C
TA = 85°C
7.7
t≤5s
TA = 25°C
15.1
Steady
State
TA = 25°C
t≤5s
TA = 25°C
Steady
State
TA = 25°C
PD
W
1.54
ID
6.8
MARKING DIAGRAM
1
UDFN6
(mCOOL])
CASE 517BG
AGMG
G
(Note: Microdot may be in either location)
PIN CONNECTIONS
A
4.9
TA = 25°C
PD
0.63
W
Pulsed Drain Current
tp = 10 ms
IDM
43
A
TJ,
TSTG
-55 to
150
°C
Source Current (Body Diode) (Note 1)
IS
1.55
A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
June, 2019 − Rev. 0
Pin 1
3.1
TA = 85°C
© Semiconductor Components Industries, LLC, 2014
D
AG = Specific Device Code
M = Date Code
G = Pb−Free Package
Power Dissipation (Note 2)
MOSFET Operating Junction and Storage
Temperature
S
1
D
1
D
2
G
3
6
D
5
D
4
S
D
S
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Publication Order Number:
NVLUS4C12N/D
NVLUS4C12N
2. Surface-mounted on FR4 board using the minimum recommended pad size,
2 oz. Cu.
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2
NVLUS4C12N
THERMAL RESISTANCE RATINGS
Symbol
Max
Junction-to-Ambient – Steady State (Note 3)
RθJA
81
Junction-to-Ambient – t ≤ 5 s (Note 3)
RθJA
40.5
Junction-to-Ambient – Steady State min Pad (Note 4)
RθJA
200
Parameter
Unit
°C/W
3. Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).
4. Surface-mounted on FR4 board using the minimum recommended pad size, 2 oz. Cu.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain-to-Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain-to-Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
ID = 250 mA, ref to 25°C
Typ
Max
Units
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
VGS = 0 V,
VDS = 24 V
Gate-to-Source Leakage Current
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
V
12
TJ = 25°C
mV/°C
1.0
TJ = 125°C
mA
10
±100
nA
2.1
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temp. Coefficient
Drain-to-Source On Resistance
Forward Transconductance
VGS(TH)/TJ
1.3
4.8
RDS(on)
gFS
mV/°C
mW
VGS = 10 V, ID = 9.0 A
7.2
9
VGS = 4.5 V, ID = 8.0 A
9.3
12
VGS = 3.7 V, ID = 5.0 A
10.9
15
VGS = 3.3 V, ID = 5.0 A
13
19
VDS = 15 V, ID = 9.0 A
39
S
1172
pF
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
CISS
COSS
CRSS
Total Gate Charge
QG(TOT)
Threshold Gate Charge
QG(TH)
Gate-to-Source Charge
QGS
Gate-to-Drain Charge
QGD
Total Gate Charge
VGS = 0 V, f = 1 MHz,
VDS = 15 V
546
26
8.4
VGS = 4.5 V, VDS = 15 V;
ID = 8.0 A
nC
1.1
3.0
2.2
QG(TOT)
VGS = 10 V, VDS = 15 V;
ID = 9.0 A
18
nC
9.4
ns
SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 6)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
VGS = 4.5 V, VDD = 15 V,
ID = 8.0 A, RG = 3 W
tf
15
14
3.5
SWITCHING CHARACTERISTICS, VGS = 10 V (Note 6)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
td(ON)
6.3
tr
14
td(OFF)
VGS = 10 V, VDD = 15 V,
ID = 9.0 A, RG = 3 W
tf
18
2.4
5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
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3
ns
NVLUS4C12N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
TJ = 25°C
0.72
1.1
V
TJ = 125°C
0.52
DRAIN-SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 1.5 A
ns
29
14.1
VGS = 0 V, dIs/dt = 100 A/ms,
IS = 1.5 A
14.9
QRR
20
nC
5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
TYPICAL CHARACTERISTICS
3.2 − 10 V
35
3.0 V
20
TJ = 25°C
15
2.6 V
10
2.4 V
5
2.0 V
0
0
0.5
1.0
1.5
2.0
25
TJ = 125°C
TJ = 25°C
20
15
10
5
2.2 V
2.5
VDS = 5 V
30
VGS = 2.8 V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
25
0
3.0
TJ = −55°C
1.0
1.5
2.0
2.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
3.0
21
17
TJ = 25°C
ID = 9 A
17
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (mW)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (mW)
19
15
VGS = 3.3 V
13
15
13
11
9
7
TJ = 25°C
3
4
5
6
7
8
9
VGS = 4.5 V
9
VGS = 10 V
7
5
10
VGS = 3.7 V
11
1
2
3
4
5
6
7
8
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
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4
9
NVLUS4C12N
TYPICAL CHARACTERISTICS
10,000
1.5
VGS = 10 V
ID = 9 A
1.4
TJ = 150°C
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (Normalized)
1.6
1.3
1000
1.2
1.1
1.0
0.9
0.7
0.6
−50
TJ = 85°C
VGS = 0 V
−25
0
25
50
75
100
125
150
VGS, GATE−TO−SOURCE VOLTAGE (V)
Ciss
1000
800
Coss
600
400
200
Crss
5
10
15
20
25
30
20
25
30
10
QT
8
6
4
Qgs
Qgd
TJ = 25°C
VGS = 10 V
VDD = 15 V
ID = 8 A
2
0
0
2
4
6
8
10
12
14
16
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
1000
IS, SOURCE CURRENT (A)
1.4
VDD = 15 V
ID = 15 A
VGS = 10 V
td(off)
100
tf
tr
td(on)
10
1
15
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
1200
1
10
Figure 5. On−Resistance Variation with
Temperature
TJ = 25°C
VGS = 0 V
0
5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1400
0
10
TJ, JUNCTION TEMPERATURE (°C)
1600
C, CAPACITANCE (pF)
100
0.8
1800
t, TIME (ns)
TJ = 125°C
10
VGS = 0 V
1.2
1.0
0.8
0.6
TJ = 125°C
0.4
TJ = 25°C
0.2
0
100
18
0.4
0.5
0.6
0.7
0.8
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
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5
NVLUS4C12N
TYPICAL CHARACTERISTICS
100
ID, DRAIN CURRENT (A)
10 ms
10
100 ms
1 ms
1
0.1
0.01
10 ms
0 V < VGS < 10 V
TA = 25°C
Single Pulse Response
RDS(on) Limit
Thermal Limit
Package Limit
0.01
0.1
dc
1
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
100
50% Duty Cycle
R(t) (°C/W)
20%
10 10%
5%
2%
1 1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 12. Thermal Response
DEVICE ORDERING INFORMATION
Device
NVLUS4C12NTAG
Package
Shipping†
UDFN6
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN6 2x2, 0.65P
CASE 517BG−01
ISSUE A
DATE 04 FEB 2010
SCALE 4:1
D
PIN ONE
REFERENCE
0.10 C
0.10 C
ÉÉ ÇÇÇ
ÉÉ
ÇÇ ÉÉÉ
B
A
ÍÍ
ÍÍ
ÍÍ
EXPOSED Cu
PLATING
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
THE TERMINALS.
1. CENTER TERMINAL LEAD IS OPTIONAL. CENTER TERMINAL
IS CONNECTED TO TERMINAL LEAD # 4.
2. LEADS 1, 2, 5 AND 6 ARE TIED TO THE FLAG.
MOLD CMPD
DETAIL B
OPTIONAL
CONSTRUCTIONS
L
L
TOP VIEW
DETAIL B
A
A3
0.10 C
DIM
A
A1
A3
b
b1
D
D2
E
E2
e
K
J
J1
L
L1
L2
L1
DETAIL A
OPTIONAL
CONSTRUCTIONS
0.08 C
NOTE 4
A1
C
SIDE VIEW
D2
DETAIL A
6X
L
SEATING
PLANE
1
L2
3
GENERIC
MARKING DIAGRAM*
e
1
b1
0.10 C A
E2
0.05 C
K
6
4
6X
B
NOTE 5
0.10 C A
0.05 C
XXMG
G
XX = Specific Device Code
M = Date Code
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”,
may or may not be present.
b
J
J1
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.25
0.35
0.51
0.61
2.00 BSC
1.00
1.20
2.00 BSC
1.10
1.30
0.65 BSC
0.15 REF
0.27 BSC
0.65 BSC
0.20
0.30
--0.10
0.20
0.30
B
NOTE 3
BOTTOM VIEW
RECOMMENDED
MOUNTING FOOTPRINT
2.30
1.10
6X
6X
0.35
0.43
1
0.60
1.25
0.35
0.34
0.65
PITCH
DOCUMENT NUMBER:
DESCRIPTION:
98AON48158E
UDFN6 2X2, 0.65P
PACKAGE
OUTLINE
0.66
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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