NVMFD5852NL
Power MOSFET
40 V, 6.9 mW, 44 A, Dual N−Channel Logic
Level, Dual SO−8FL
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Designs
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
NVMFD5852NLWF − Wettable Flanks Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
This is a Pb−Free Device
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V(BR)DSS
Symbol
6.9 mW @ 10 V
44 A
12.0 mW @ 4.5 V
Dual N−Channel
Value
Unit
Drain−to−Source Voltage
VDSS
40
V
Gate−to−Source Voltage
VGS
"20
V
ID
44
A
Continuous Drain Current RYJ−mb (Notes 1,
2, 3, 4)
Power Dissipation
RYJ−mb (Notes 1, 2, 3)
Continuous Drain Current RqJA (Notes 1, 3
& 4)
Power Dissipation
RqJA (Notes 1 & 3)
Pulsed Drain Current
Tmb = 25°C
Steady
State
Tmb = 100°C
Tmb = 25°C
Steady
State
27
PD
Operating Junction and Storage Temperature
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VGS = 10 V, IL(pk) = 40 A,
L = 0.1 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
MARKING DIAGRAM
A
3.2
W
1.6
IDM
329
A
TJ, Tstg
−55 to
175
°C
IS
40
A
EAS
80
mJ
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Junction−to−Mounting Board (top) − Steady
State (Notes 2, 3)
Junction−to−Ambient − Steady State (Note 3)
Symbol
Value
RYJ−mb
5.6
RqJA
September, 2014 − Rev. 6
5852xx
AYWZZ
D1
D1
D2
D2
D2 D2
5852NL = Specific Device Code
for NVMFD5852NL
5852LW = Specific Device Code
for NVMFD5852NLWF
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
ORDERING INFORMATION
Package
Shipping†
NVMFD5852NLT1G
DFN8
(Pb−Free)
1500 / Tape &
Reel
°C/W
NVMFD5852NLWFT1G
DFN8
(Pb−Free)
1500 / Tape &
Reel
47
1
S1
G1
S2
G2
Unit
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
4. Maximum current for pulses as long as 1 second are higher but are dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2014
DFN8 5x6
(SO8FL)
CASE 506BT
Device
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
D1 D1
1
10.6
PD
S2
S1
W
15
ID
TA = 100°C
TA = 25°C, tp = 10 ms
G2
G1
13
TA = 100°C
TA = 25°C
D2
D1
31
Tmb = 100°C
TA = 25°C
ID MAX
40 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
RDS(on) MAX
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NVMFD5852NL/D
NVMFD5852NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
40
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
VGS = 0 V,
VDS = 40 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
100
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
Gate−to−Source Leakage Current
V
37.3
±100
mA
nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
Forward Transconductance
gFS
1.4
2.4
6.3
V
mV/°C
VGS = 10 V, ID = 20 A
5.3
6.9
VGS = 4.5 V, ID = 20 A
8.7
12
VDS = 5 V, ID = 5 A
24
S
pF
mW
CHARGES AND CAPACITANCES
Input Capacitance
Ciss
1800
Output Capacitance
Coss
240
Reverse Transfer Capacitance
Crss
180
Total Gate Charge
QG(TOT)
20
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
VGS = 0 V, f = 1.0 MHz, VDS = 25 V
VGS = 4.5 V, VDS = 32 V,
ID = 20 A
nC
1.5
5.5
10.9
VGS = 10 V, VDS = 32V, ID = 20 A
36
nC
td(on)
12
ns
tr
52
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(off)
VGS = 4.5 V, VDS = 32 V,
ID = 20 A, RG = 2.5 W
21
tf
13
td(on)
12
tr
td(off)
VGS = 10 V, VDS = 32 V,
ID = 20 A, RG = 2.5 W
tf
ns
8.0
27
5.0
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.84
TJ = 125°C
0.69
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 20 A
22.3
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 20 A
QRR
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2
V
ns
12.8
9.4
15.2
5. Pulse Test: pulse width = 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
1.1
nC
NVMFD5852NL
TYPICAL CHARACTERISTICS
150
VDS ≥ 10 V
5.0 V
125
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
150
7.0 V
10 V
TJ = 25°C
100
4.4 V
75
4.0 V
50
3.6 V
3.4 V
25
125
100
75
50
TJ = 25°C
25
TJ = 125°C
3.0 V
0
1
3
2
5
4
3.0
3.5
4.0
4.5
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.018
ID = 20 A
TJ = 25°C
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.002
3
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
5.0
0.0200
TJ = 25°C
0.0175
0.0150
VGS = 4.5 V
0.0125
0.0100
0.0075
VGS = 10 V
0.0050
0.0025
0
0
25
75
50
100
125
150
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. VGS
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.2
2.0
2.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.020
2
2.0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
100,000
VGS = 0 V
ID = 20 A
VGS = 10 V
1.8
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
TJ = −55°C
0
1.6
1.4
1.2
1.0
10,000
TJ = 150°C
TJ = 125°C
1,000
0.8
0.6
−50 −25
100
0
25
50
75
100
125
150
175
5
10
15
20
25
30
35
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
40
NVMFD5852NL
TYPICAL CHARACTERISTICS
VGS = 0 V
TJ = 25°C
Ciss
2000
VGS, GATE−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
2500
1500
1000
Coss
500
Crss
0
0
10
20
30
QT
8
6
Qgs
Qgd
4
TJ = 25°C
VDS = 32 V
ID = 20 A
2
0
0
40
5
10
15
20
25
30
35
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
40
100
1000
IS, SOURCE CURRENT (A)
VDS = 32 V
ID = 20 A
VGS = 4.5 V
tr
tf
td(off)
100
td(on)
10
1
10
VGS = 0 V
75
50
TJ = 25°C
25
0
0.60 0.65 0.70
100
0.75 0.80 0.85 0.90 0.95 1.00 1.05
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
10 ms
ID, DRAIN CURRENT (A)
t, TIME (ns)
10
10
1
0.1
100 ms
1 ms
VGS = 10 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
0.1
10 ms
dc
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
100
NVMFD5852NL
TYPICAL CHARACTERISTICS
100
RqJA (°C/W)
Duty Cycle = 50%
10 20%
10%
5%
1
2%
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.1
0.01
PULSE TIME (sec)
Figure 12. Thermal Response
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5
1
10
100
1000
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE F
1
2X
SCALE 2:1
0.20 C
D
A
B
D1
8
7
6
ÉÉ
ÉÉ
ÉÉ
PIN ONE
IDENTIFIER
NOTE 7
1
2
2X
0.20 C
5
DATE 23 NOV 2021
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
E1 E
4X
h
3
4
c
TOP VIEW
A1
0.10 C
A
DETAIL B
0.10 C
NOTE 4
C
SIDE VIEW
DETAIL A
D2
D3
4X
e
1
SEATING
PLANE
NOTE 6
ALTERNATE
CONSTRUCTION
DETAIL A
L
K
4
DIM
A
A1
b
b1
c
D
D1
D2
D3
E
E1
E2
e
G
h
K
K1
L
M
N
MILLIMETERS
NOM
MIN
MAX
−−−
0.90
1.10
−−−
−−−
0.05
0.33
0.42
0.51
0.33
0.42
0.51
0.20
−−−
0.33
5.15 BSC
4.70
4.90
5.10
3.90
4.10
4.30
1.50
1.70
1.90
6.15 BSC
5.70
5.90
6.10
3.90
4.15
4.40
1.27 BSC
0.45
0.55
0.65
−−−
−−−
12 _
0.51
−−−
−−−
0.56
−−−
−−−
0.48
0.61
0.71
3.25
3.50
3.75
1.80
2.00
2.20
SOLDERING FOOTPRINT*
DETAIL B
4.56
M
4X
b1
N
4X
8
G
5
8X
2X
2X
2.08
8X
E2
0.75
0.56
b
K1
BOTTOM VIEW
0.10
C A B
0.05
C
GENERIC
MARKING DIAGRAM*
1
XXXXXX
AYWZZ
NOTE 3
4.84
4X
6.59
3.70
0.70
4X
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
1.40
2.30
1.00
1.27
PITCH
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON50417E
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)
PAGE 1 OF 1
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