NVMFD5C466NL
MOSFET – Power, Dual
N-Channel
40 V, 7.4 mW, 52 A
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFD5C466NLWF − Wettable Flank Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(ON) MAX
7.4 m @ 10 V
40 V
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current RJC
(Notes 1, 2, 3)
TC = 25°C
Power Dissipation
RJC (Notes 1, 2)
Continuous Drain
Current RJA
(Notes 1, 2, 3)
Steady
State
TC = 25°C
Power Dissipation
RJA (Notes 1, 2)
Pulsed Drain Current
Value
Unit
VDSS
40
V
VGS
±20
V
ID
52
A
Steady
State
PD
ID
PD
D1 D1
W
3.0
1.5
198
A
TJ, Tstg
−55 to
+175
°C
IS
31.3
A
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, IL(pk) = 3 A)
EAS
72
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Source Current (Body Diode)
MARKING
DIAGRAM
A
15
IDM
Operating Junction and Storage Temperature
Range
S2
S1
W
38
11
TA = 100°C
TA = 25°C, tp = 10 s
G2
G1
19
TA = 100°C
TA = 25°C
D2
D1
37
TC = 100°C
TA = 25°C
Dual N−Channel
Symbol
TC = 100°C
52 A
12.6 m @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
ID MAX
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1
DFN8 5x6
(SO8FL)
CASE 506BT
A
Y
W
ZZ
S1
G1
S2
G2
XXXXXX
AYWZZ
D1
D1
D2
D2
D2 D2
= Assembly Location
= Year
= Work Week
= Lot Traceability
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
°C/W
Junction−to−Case − Steady State
RJC
4
Junction−to−Ambient − Steady State (Note 2)
RJA
47.3
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2017
July, 2019 − Rev. 4
1
Publication Order Number:
NVMFD5C466NL/D
NVMFD5C466NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 A
40
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
29
VGS = 0 V,
VDS = 40 V
mV/°C
TJ = 25 °C
10
TJ = 125°C
250
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 30 A
100
A
nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
1.2
2.2
−4.7
VGS = 10 V
ID = 10 A
6.2
7.4
VGS = 4.5 V
ID = 10 A
10
12.6
gFS
VDS = 15 V, ID = 25 A
V
mV/°C
33
m
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
997
VGS = 0 V, f = 1 MHz, VDS = 25 V
354
pF
13
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 32 V; ID = 25 A
7.0
Total Gate Charge
QG(TOT)
VGS = 10 V, VDS = 32 V; ID = 25 A
16
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Plateau Voltage
VGP
3.3
td(ON)
10
1.5
VGS = 4.5 V, VDS = 32 V; ID = 25 A
nC
2.3
2.2
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 4.5 V, VDS = 32 V,
ID = 25 A, RG = 1.0
tf
67
ns
26
60
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
VSD
VGS = 0 V,
IS = 10 A
TJ = 25°C
0.9
TJ = 125°C
0.7
tRR
ta
tb
1.2
V
20
VGS = 0 V, dIS/dt = 100 A/s,
IS = 25 A
QRR
10
ns
10
8
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 s, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFD5C466NL
TYPICAL CHARACTERISTICS
100
VGS = 10 to 5 V
ID, DRAIN CURRENT (A)
50
3.8 V
40
3.6 V
30
3.4 V
20
3.2 V
10
70
60
50
40
30
TJ = 25°C
20
0.5
1.0
1.5
2.0
2.5
0
3.0
0
TJ = −55°C
2
1
3
4
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
20
15
10
5
4
5
6
7
8
9
10
6
5
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 10 A
TJ = 25°C
3
TJ = 125°C
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (m)
0
25
0
80
10
14
13
TJ = 25°C
VGS = 4.5 V
12
11
10
9
8
7
VGS = 10 V
6
5
4
5
10
15
20
25
30
40
35
45
50
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.1
2.0
ID = 10 A
1.9
V
GS = 10 V
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
−50 −25
0
100K
TJ = 150°C
10K
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (m)
0
VDS = 10 V
90
4.5 V
60
ID, DRAIN CURRENT (A)
70
TJ = 125°C
1K
TJ = 85°C
100
TJ = 25°C
10
25
50
75
100
125
150
1
175
5
10
15
20
25
30
35
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
40
NVMFD5C466NL
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
10K
Ciss
1K
Coss
100
Crss
10
1
TJ = 25°C
VGS = 0 V
f = 1 MHz
0
5
10
15
20
25
30
35
40
5
Qgs
4
10
Qgd
3
2
VDS = 32 V
ID = 25 A
1
0
0
10
IS, SOURCE CURRENT (A)
t, TIME (ns)
TJ = 25°C
6
1
2
3
4
5
6
7
8
9
Figure 8. Gate−to−Source vs. Total Charge
td(off)
td(on)
VGS = 4.5 V
VDS = 32 V
ID = 25 A
1
10
TJ = 125°C
1
0.1
100
10
VGS = 0 V
TJ = 25°C
0.3
0.4
0.5
0.6
TJ = −55°C
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE ()
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
TC = 25°C
VGS ≤ 10 V
Single Pulse
TJ(initial) = 25°C
10
IPEAK (A)
ID, DRAIN CURRENT (A)
7
Figure 7. Capacitance Variation
tf
100
8
Qg, TOTAL GATE CHARGE (nC)
100 tr
1000
QT
9
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1000
1
10
10 s
10
TJ(initial) = 100°C
1
1
0.1
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
10
0.5 ms
1 ms
10 ms
100
1000
0.1
1.0E−05
1.0E−04
1.0E−03
1.0E−02
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NVMFD5C466NL
TYPICAL CHARACTERISTICS
100
50% Duty Cycle
R(t) (°C/W)
10
1
20%
10%
5%
2%
1%
0.1
0.01
Single Pulse
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Marking
Package
Shipping†
NVMFD5C466NLT1G
5C466L
DFN8
(Pb−Free)
1500 / Tape & Reel
NVMFD5C466NLWFT1G
466LWF
DFN8
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE F
1
2X
SCALE 2:1
0.20 C
D
A
B
D1
8
7
6
ÉÉ
ÉÉ
ÉÉ
PIN ONE
IDENTIFIER
NOTE 7
1
2
2X
0.20 C
5
DATE 23 NOV 2021
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
E1 E
4X
h
3
4
c
TOP VIEW
A1
0.10 C
A
DETAIL B
0.10 C
NOTE 4
C
SIDE VIEW
DETAIL A
D2
D3
4X
e
1
SEATING
PLANE
NOTE 6
ALTERNATE
CONSTRUCTION
DETAIL A
L
K
4
DIM
A
A1
b
b1
c
D
D1
D2
D3
E
E1
E2
e
G
h
K
K1
L
M
N
MILLIMETERS
NOM
MIN
MAX
−−−
0.90
1.10
−−−
−−−
0.05
0.33
0.42
0.51
0.33
0.42
0.51
0.20
−−−
0.33
5.15 BSC
4.70
4.90
5.10
3.90
4.10
4.30
1.50
1.70
1.90
6.15 BSC
5.70
5.90
6.10
3.90
4.15
4.40
1.27 BSC
0.45
0.55
0.65
−−−
−−−
12 _
0.51
−−−
−−−
0.56
−−−
−−−
0.48
0.61
0.71
3.25
3.50
3.75
1.80
2.00
2.20
SOLDERING FOOTPRINT*
DETAIL B
4.56
M
4X
b1
N
4X
8
G
5
8X
2X
2X
2.08
8X
E2
0.75
0.56
b
K1
BOTTOM VIEW
0.10
C A B
0.05
C
GENERIC
MARKING DIAGRAM*
1
XXXXXX
AYWZZ
NOTE 3
4.84
4X
6.59
3.70
0.70
4X
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
1.40
2.30
1.00
1.27
PITCH
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON50417E
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)
PAGE 1 OF 1
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