NVMFD5C478N
Power MOSFET
40 V, 17.0 mW, 27 A, Dual N−Channel
Features
•
•
•
•
•
•
Small Footprint (5 x 6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
NVMFD5C478NWF − Wettable Flanks Product
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(on) MAX
ID MAX
40 V
17.0 mW @ 10 V
27 A
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current RqJC
(Notes 1, 2, 3, 4)
TC = 25°C
Power Dissipation
RqJC (Notes 1, 2, 3)
Continuous Drain
Current RqJA
(Notes 1 & 3, 4)
Steady
State
Value
Unit
VDSS
40
V
VGS
±20
V
ID
27
A
TC = 100°C
TC = 25°C
Steady
State
PD
Pulsed Drain Current
W
23
ID
PD
S2
PIN CONNECTION &
MARKING DIAGRAM
W
3.1
1.5
1
IDM
90
A
−55 to
+175
°C
IS
19
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 1.4 A)
EAS
48
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Source Current (Body Diode)
S1
6.9
TJ, Tstg
TA = 25°C, tp = 10 ms
D2
G2
A
9.8
TA = 100°C
Operating Junction and Storage Temperature
Dual−Channel
G1
12
TA = 100°C
TA = 25°C
D1
19
TC = 100°C
TA = 25°C
Power Dissipation
RqJA (Notes 1, 3)
Symbol
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
DFN8, 5x6
(S08FL)
CASE 506BT
1 D1 D1
S1
G1 XXXXXX
AYWZZ
S2
G2
D2 D2
D1
D1
D2
D2
XXXXXX = 5C478N (NVMFD5C478N) or
478NWF (NVMFD5C478NWF)
A
= Assembly Location
Y
= Year
ZZ
= Lot Traceability
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Symbol
Value
Unit
Junction−to−Case − Steady State (Note 3)
RqJC
6.5
°C/W
Junction−to−Ambient − Steady State (Note 3)
RqJA
48.8
Parameter
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
4. Continuous DC current rating. Maximum current for pulses as long as 1
second is higher but is dependent on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2017
December, 2018 − Rev. 1
1
Publication Order Number:
NVMFD5C478N/D
NVMFD5C478N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
V(BR)DSS
VGS = 0 V, ID = 250 mA
40
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
VGS = 0 V,
VDS = 40 V
V
TJ = 25°C
10
TJ = 125°C
250
100
mA
IGSS
VDS = 0 V, VGS = 20 V
nA
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 20 mA
Drain−to−Source On Resistance
RDS(on)
VGS = 10 V, ID = 7.5 A
14
gFS
VDS = 3 V, ID = 7.5 A
2
S
325
pF
ON CHARACTERISTICS (Note 5)
Forward Transconductance
2.5
3.5
V
17
mW
CHARGES AND CAPACITANCES
Ciss
Input Capacitance
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
VGS = 0 V, f = 1.0 MHz,
VDS = 25 V
165
10
Total Gate Charge
QG(TOT)
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
1.2
td(on)
7
VGS = 10 V, VDS = 32 V, ID = 7.5 A
6.3
nC
1.3
nC
2.0
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(off)
VGS = 10 V, VDS = 32 V,
ID = 7.5 A, RG = 1 W
tf
ns
13
14
4.5
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
VGS = 0 V,
IS = 7.5 A
TJ = 25°C
0.84
TJ = 125°C
0.72
tRR
18
Charge Time
ta
7.0
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V, dlS/dt = 100 A/ms,
IS = 7.5 A
QRR
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2
V
ns
11
6
5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
1.2
nC
NVMFD5C478N
TYPICAL CHARACTERISTICS
30
ID, DRAIN CURRENT (A)
20
15
10
5V
5
4V
0
1
2
3
20
15
10
TJ = 25°C
5
TJ = 125°C
3
6
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
90
80
70
60
50
40
30
20
10
0
5
6
8
7
9
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
20
TJ = 25°C
18
16
VGS = 10 V
14
12
10
8
6
4
2
0
0
5
10
20
15
25
30
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10K
1.9
VGS = 10 V
ID = 7.5 A
TJ = 150°C
IDSS, LEAKAGE (nA)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
5
VGS, GATE−TO−SOURCE VOLTAGE (V)
TJ = 25°C
ID = 7.5 A
1.7
TJ = −55°C
4
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
100
4
25
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
ID, DRAIN CURRENT (A)
VDS = 10 V
25
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
30
6V
7 V to 10 V
1.5
1.3
1.1
1K
TJ = 125°C
100
TJ = 85°C
0.9
0.7
−50
−25
0
25
50
75
100
125
150
175
10
5
10
15
20
25
30
35
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
40
NVMFD5C478N
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
10,000
1000
CISS
100
COSS
10
CRSS
VGS = 0 V
TJ = 25°C
f = 1 MHz
1
0
5
10
15
20
30
25
35
40
10
9
8
7
6
QGD
QGS
5
4
3
VDS = 32 V
ID = 7.5 A
TJ = 25°C
2
1
0
0
2
1
3
6
5
4
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage vs. Total
Charge
100
7
8.2
IS, SOURCE CURRENT (A)
VGS = 0 V
tr
t, TIME (ns)
td(off)
10
td(on)
tf
1
VGS = 10 V
VDS = 32 V
1
TJ = 125°C
2.2
TJ = 25°C
TJ = −55°C
0.5
0.6
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
TC = 25°C
VGS ≤ 10 V
Single Pulse
100
TJ (initial) = 25°C
10
10 ms
IPEAK, (A)
ID, DRAIN CURRENT (A)
4.2
0.2
10
1000
10
1
0.1
6.2
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
10
TJ (initial) = 100°C
1
0.5 ms
1 ms
10 ms
0.1
100
1000
0.00001
0.0001
0.001
VDS, DRAIN−TO−SOURCE VOLTAGE(V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
0.01
NVMFD5C478N
TYPICAL CHARACTERISTICS
100
50% Duty Cycle
RqJA (°C/W)
10
1
20%
10%
5%
2%
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
Marking
Package
Shipping†
NVMFD5C478NT1G
5C478N
DFN8
(Pb−Free)
1500 / Tape & Reel
NVMFD5C478NWFT1G
478NWF
DFN8
(Pb−Free)
1500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE F
1
2X
SCALE 2:1
0.20 C
D
A
B
D1
8
7
6
ÉÉ
ÉÉ
ÉÉ
PIN ONE
IDENTIFIER
NOTE 7
1
2
2X
0.20 C
5
DATE 23 NOV 2021
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
E1 E
4X
h
3
4
c
TOP VIEW
A1
0.10 C
A
DETAIL B
0.10 C
NOTE 4
C
SIDE VIEW
DETAIL A
D2
D3
4X
e
1
SEATING
PLANE
NOTE 6
ALTERNATE
CONSTRUCTION
DETAIL A
L
K
4
DIM
A
A1
b
b1
c
D
D1
D2
D3
E
E1
E2
e
G
h
K
K1
L
M
N
MILLIMETERS
NOM
MIN
MAX
−−−
0.90
1.10
−−−
−−−
0.05
0.33
0.42
0.51
0.33
0.42
0.51
0.20
−−−
0.33
5.15 BSC
4.70
4.90
5.10
3.90
4.10
4.30
1.50
1.70
1.90
6.15 BSC
5.70
5.90
6.10
3.90
4.15
4.40
1.27 BSC
0.45
0.55
0.65
−−−
−−−
12 _
0.51
−−−
−−−
0.56
−−−
−−−
0.48
0.61
0.71
3.25
3.50
3.75
1.80
2.00
2.20
SOLDERING FOOTPRINT*
DETAIL B
4.56
M
4X
b1
N
4X
8
G
5
8X
2X
2X
2.08
8X
E2
0.75
0.56
b
K1
BOTTOM VIEW
0.10
C A B
0.05
C
GENERIC
MARKING DIAGRAM*
1
XXXXXX
AYWZZ
NOTE 3
4.84
4X
6.59
3.70
0.70
4X
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
1.40
2.30
1.00
1.27
PITCH
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON50417E
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)
PAGE 1 OF 1
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