NVMFD5C668NLT1G

NVMFD5C668NL MOSFET – Power, Dual N-Channel 60 V, 6.5 mW, 68 A Features • • • • • • Small Footprint (5x6 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses NVMFD5C668NLWF − Wettable Flank Option for Enhanced Optical Inspection AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant www.onsemi.com V(BR)DSS Unit Drain−to−Source Voltage VDSS 60 V Gate−to−Source Voltage VGS ±20 V ID 68 A Power Dissipation RqJC (Notes 1, 2) Continuous Drain Current RqJA (Notes 1, 2, 3) Steady State TC = 100°C TC = 25°C TC = 100°C TA = 25°C Power Dissipation RqJA (Notes 1 & 2) Pulsed Drain Current Steady State ID D1 D1 PD W 3.0 1.5 IDM 454 A TJ, Tstg −55 to + 175 °C IS 48 A Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, IL(pk) = 3.22 A) EAS 205 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C TA = 25°C, tp = 10 ms Source Current (Body Diode) MARKING DIAGRAM A 15.5 11 TA = 100°C Operating Junction and Storage Temperature S2 S1 W 57.5 29 TA = 100°C TA = 25°C G2 G1 48 PD 68 A D2 D1 Value TC = 25°C 9.2 mW @ 4.5 V Dual N−Channel Symbol Continuous Drain Current RqJC (Notes 1, 2, 3) ID MAX 6.5 mW @ 10 V 60 V MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter RDS(ON) MAX Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1 DFN8 5x6 (SO8FL) CASE 506BT S1 G1 S2 G2 XXXXXX AYWZZ D1 D1 D2 D2 D2 D2 XXXXXX = 5C668L (NVMFD5C668NL) or 668LWF (NVMFD5C668NLWF) A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit Junction−to−Case − Steady State RqJC 2.6 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 50.26 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2017 July, 2019 − Rev. 0 1 Publication Order Number: NVMFD5C668NL/D NVMFD5C668NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 60 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 28 VGS = 0 V, VDS = 60 V mV/°C TJ = 25°C 10 TJ = 125°C 250 IGSS VDS = 0 V, VGS = 20 V VGS(TH) VGS = VDS, ID = 50 mA 100 mA nA ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance Forward Transconductance RDS(on) 1.2 2.0 −5.3 VGS = 10 V ID = 20 A 5.4 6.5 VGS = 4.5 V ID = 20 A 7.4 9.2 gFS VDS = 15 V, ID = 20 A V mV/°C 61 mW S CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 1440 VGS = 0 V, f = 1 MHz, VDS = 25 V 800 pF 14 Total Gate Charge QG(TOT) VGS = 4.5 V, VDS = 48 V; ID = 20 A 9.8 Total Gate Charge QG(TOT) VGS = 10 V, VDS = 48 V; ID = 20 A 21.3 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Plateau Voltage VGP 2.9 td(ON) 10 2.5 VGS = 10 V, VDS = 48 V; ID = 20 A nC 4.3 2.1 V SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(OFF) VGS = 10 V, VDS = 48 V, ID = 20 A, RG = 1.0 W tf 22 ns 40 7.0 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 20 A TJ = 25°C 0.85 TJ = 125°C 0.73 tRR ta tb 1.2 V 42 VGS = 0 V, dIS/dt = 100 A/ms, IS = 20 A QRR 20 ns 22 32 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NVMFD5C668NL TYPICAL CHARACTERISTICS 70 35 10 V to 3.6 V ID, DRAIN CURRENT (A) 50 3.2 V 40 3.0 V 30 2.8 V 20 25 20 15 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.6 1.4 1.8 2.0 TJ = 25°C TJ = −55°C 0 4 5 Figure 2. Transfer Characteristics 12 10 8 6 4 2 4 3 5 6 7 9 8 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 12 11 TJ = 25°C 10 9 8 7 VGS = 4.5 V VGS = 10 V 6 5 4 3 2 1 0 10 15 25 20 30 35 40 45 50 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 100K VGS = 10 V ID = 20 A IDSS, LEAKAGE (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE 3 Figure 1. On−Region Characteristics 14 1.7 2 VGS, GATE−TO−SOURCE VOLTAGE (V) TJ = 25°C ID = 5 A 1.9 1 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 16 2 TJ = 125°C 10 10 0 VDS = 10 V 30 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) ID, DRAIN CURRENT (A) 60 1.5 1.3 1.1 TJ = 150°C 10K TJ = 125°C 1K TJ = 85°C 100 0.9 0.7 −50 −25 0 25 50 75 100 125 150 175 10 10 15 20 25 30 35 40 45 50 55 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 60 NVMFD5C668NL TYPICAL CHARACTERISTICS VGS, GATE−TO−SOURCE VOLTAGE (V) 10000 C, CAPACITANCE (pF) CISS 1000 COSS 100 10 CRSS VGS = 0 V TJ = 25°C f = 1 MHz 1 0 20 10 30 40 50 60 10 9 8 7 6 5 QGS 4 3 VDS = 48 V ID = 20 A TJ = 25°C 2 1 0 0 20 t, TIME (ns) IS, SOURCE CURRENT (A) td(off) tf td(on) 10 VGS = 10 V VDS = 48 V 1 25 20 Figure 8. Gate−to−Source Voltage vs. Total Charge tr VGS = 0 V 16 14 12 10 8 6 4 TJ = 125°C TJ = 25°C TJ = −55°C 2 0 0.5 10 0.6 0.7 0.8 0.9 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 100 1000 100 IPEAK, (A) 10 10 0.1 15 Figure 7. Capacitance Variation 100 1 10 QG, TOTAL GATE CHARGE (nC) 18 ID, DRAIN CURRENT (A) 5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1000 1 QGD 10 ms TC = 25°C VGS ≤ 10 V Single Pulse 1 RDS(on) Limit Thermal Limit Package Limit 0.1 1 10 TJ (initial) = 25°C TJ (initial) = 100°C 0.5 ms 1 ms 10 ms 100 0.1 0.00001 1000 0.0001 0.001 VDS, DRAIN−TO−SOURCE VOLTAGE(V) TIME IN AVALANCHE (s) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. IPEAK vs. Time in Avalanche www.onsemi.com 4 0.01 NVMFD5C668NL TYPICAL CHARACTERISTICS 100 50% Duty Cycle RqJA (°C/W) 10 1 20% 10% 5% 2% 1% 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE TIME (sec) Figure 13. Thermal Characteristics DEVICE ORDERING INFORMATION Marking Package Shipping† NVMFD5C668NLT1G 5C668L DFN8 (Pb−Free) 1500 / Tape & Reel NVMFD5C668NLWFT1G 668LWF DFN8 (Pb−Free, Wettable Flanks) 1500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual) CASE 506BT ISSUE F 1 2X SCALE 2:1 0.20 C D A B D1 8 7 6 ÉÉ ÉÉ ÉÉ PIN ONE IDENTIFIER NOTE 7 1 2 2X 0.20 C 5 DATE 23 NOV 2021 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP. 4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. 7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA. E1 E 4X h 3 4 c TOP VIEW A1 0.10 C A DETAIL B 0.10 C NOTE 4 C SIDE VIEW DETAIL A D2 D3 4X e 1 SEATING PLANE NOTE 6 ALTERNATE CONSTRUCTION DETAIL A L K 4 DIM A A1 b b1 c D D1 D2 D3 E E1 E2 e G h K K1 L M N MILLIMETERS NOM MIN MAX −−− 0.90 1.10 −−− −−− 0.05 0.33 0.42 0.51 0.33 0.42 0.51 0.20 −−− 0.33 5.15 BSC 4.70 4.90 5.10 3.90 4.10 4.30 1.50 1.70 1.90 6.15 BSC 5.70 5.90 6.10 3.90 4.15 4.40 1.27 BSC 0.45 0.55 0.65 −−− −−− 12 _ 0.51 −−− −−− 0.56 −−− −−− 0.48 0.61 0.71 3.25 3.50 3.75 1.80 2.00 2.20 SOLDERING FOOTPRINT* DETAIL B 4.56 M 4X b1 N 4X 8 G 5 8X 2X 2X 2.08 8X E2 0.75 0.56 b K1 BOTTOM VIEW 0.10 C A B 0.05 C GENERIC MARKING DIAGRAM* 1 XXXXXX AYWZZ NOTE 3 4.84 4X 6.59 3.70 0.70 4X XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability 1.40 2.30 1.00 1.27 PITCH 5.55 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON50417E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL) PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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