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onsemi and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
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regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
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Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
NVMFD6H840NL
Power MOSFET
80 V, 6.9 mW, 74 A, Dual N−Channel
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFD6H840NLWF − Wettable Flank Option for Enhanced
Optical Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(ON) MAX
ID MAX
6.9 m @ 10 V
80 V
74 A
8.8 m @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current RJC
(Notes 1, 2, 3)
TC = 25°C
Power Dissipation
RJC (Notes 1, 2)
Continuous Drain
Current RJA
(Notes 1, 2, 3)
Steady
State
Pulsed Drain Current
Value
Unit
VDSS
80
V
VGS
±20
V
ID
74
A
TC = 100°C
TC = 25°C
Steady
State
PD
W
90
ID
PD
1.5
D1 D1
TJ, Tstg
−55 to
+175
°C
IS
75
A
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, IL(pk) = 4.7 A)
EAS
297
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
A
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
MARKING
DIAGRAM
W
3.1
336
Source Current (Body Diode)
S2
S1
A
14
IDM
Operating Junction and Storage Temperature
Range
G2
10
TA = 100°C
TA = 25°C, tp = 10 s
D2
G1
45
TA = 100°C
TA = 25°C
Dual N−Channel
D1
52
TC = 100°C
TA = 25°C
Power Dissipation
RJA (Notes 1, 2)
Symbol
Symbol
Value
Unit
Junction−to−Case − Steady State
RJC
1.67
°C/W
Junction−to−Ambient − Steady State (Note 2)
RJA
48.7
1
DFN8 5x6
(SO8FL)
CASE 506BT
A
Y
W
ZZ
S1
G1
S2
G2
XXXXXX
AYWZZ
D1
D1
D2
D2
D2 D2
= Assembly Location
= Year
= Work Week
= Lot Traceability
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2019
April, 2019 − Rev. 0
1
Publication Order Number:
NVMFD6H840NL/D
NVMFD6H840NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 A
80
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
45.9
VGS = 0 V,
VDS = 80 V
mV/°C
TJ = 25 °C
10
TJ = 125°C
250
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 96 A
100
A
nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
1.2
2.0
−4.9
VGS = 10 V
ID = 20 A
5.7
6.9
VGS = 4.5 V
ID = 20 A
7.0
8.8
gFS
VDS = 5 V, ID = 20 A
V
mV/°C
99
m
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
2002
VGS = 0 V, f = 1 MHz, VDS = 40 V
249
pF
11
Total Gate Charge
QG(TOT)
VGS = 10 V, VDS = 40 V; ID = 20 A
Total Gate Charge
QG(TOT)
15
Threshold Gate Charge
QG(TH)
3.0
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
5.3
Plateau Voltage
VGP
2.8
td(ON)
15
VGS = 4.5 V, VDS = 40 V; ID = 20 A
32
nC
5.1
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 4.5 V, VDS = 64 V,
ID = 20 A, RG = 2.5
tf
34
ns
52
22
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
VSD
VGS = 0 V,
IS = 20 A
TJ = 25°C
0.8
TJ = 125°C
0.7
tRR
ta
tb
1.2
V
45
VGS = 0 V, dIS/dt = 100 A/s,
IS = 20 A
QRR
24
ns
22
50
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 s, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFD6H840NL
TYPICAL CHARACTERISTICS
3.2 V
10 to 3.4 V
60
50
2.8 V
40
30
2.6 V
20
0
0
1
3
2
4
5
7
6
50
40
30
0
8
TJ = 125°C
0
0.5
1.0
1.5
TJ = −55°C
2.0
2.5
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
8
6
4
5
4
6
7
8
9
10
4.0
3.5
3.0
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
ID = 20 A
TJ = 25°C
3
TJ = 25°C
20
10
10
2
VDS = 10 V
60
VGS = 2.4 V
10
8
TJ = 25°C
VGS = 4.5 V
7
6
VGS = 10 V
5
4
10
20
40
30
50
60
70
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.5
1000
ID = 20 A
VGS = 10 V
TJ = 175°C
100
2.0
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (m)
70
RDS(on), DRAIN−TO−SOURCE RESISTANCE (m)
ID, DRAIN CURRENT (A)
70
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
80
3.0 V
ID, DRAIN CURRENT (A)
80
1.5
1.0
TJ = 150°C
TJ = 125°C
10
TJ = 85°C
1
0.1
TJ = 25°C
0.01
0.5
−50 −25
0
25
50
75
100
125
150
0.001
175
5
15
25
35
45
55
65
75
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NVMFD6H840NL
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
10K
C, CAPACITANCE (pF)
Ciss
1K
Coss
100
1
Crss
TJ = 25°C
VGS = 0 V
f = 1 MHz
0
1000
10
20
30
40
50
60
80
6
5
4
QGS
QGD
3
2
1
0
10
5
0
15
20
25
Figure 8. Gate−to−Source vs. Total Charge
VGS = 4.5 V
VDS = 64 V
ID = 20 A
30
VGS = 0 V
td(off)
tf
tr
1
10
10
1
100
TJ = 125°C
0.3
0.4
TJ = 25°C
0.5
0.6
TJ = −55°C
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE ()
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
IPEAK, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
7
Figure 7. Capacitance Variation
10
100
10
TC = 25°C
VGS ≤ 10 V
Single Pulse
1
0.1
8
QG, TOTAL GATE CHARGE (nC)
td(on)
1
VDS = 40 V
ID = 20 A
TJ = 25°C
9
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
100
t, TIME (ns)
70
IS, SOURCE CURRENT (A)
10
10
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
10
10 s
0.5 ms
1 ms
10 ms
100
1000
TJ(initial) = 25°C
10
TJ(initial) = 100°C
1
0.00001
0.0001
0.001
0.01
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TAV, TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NVMFD6H840NL
TYPICAL CHARACTERISTICS
100
50% Duty Cycle
R(t) (°C/W)
10
1
20%
10%
5%
2%
1%
0.1
0.01
Single Pulse
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Marking
Package
Shipping†
NVMFD6H840NLT1G
6H840L
DFN8
(Pb−Free)
1500 / Tape & Reel
NVMFD6H840NLWFT1G
840LWF
DFN8
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
DATE 26 FEB 2013
1
SCALE 2:1
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
0.20 C
D
A
B
D1
8
7
6
ÉÉ
ÉÉ
PIN ONE
IDENTIFIER
NOTE 7
1
2
2X
0.20 C
5
E1 E
4X
c
3
GENERIC
MARKING DIAGRAM*
h
A1
4
1
XXXXXX
AYWZZ
TOP VIEW
0.10 C
DETAIL A
A
0.10 C
NOTE 4
C
SIDE VIEW
DETAIL A
D2
D3
4X
e
1
L
K
4
DETAIL B
4X
b1
N
4X
G
*This information is generic. Please refer
to device data sheet for actual part
marking.
MILLIMETERS
MAX
MIN
MAX
−−−
0.90
1.10
−−−
−−−
0.05
0.33
0.42
0.51
0.33
0.42
0.51
0.20
−−−
0.33
5.15 BSC
4.70
4.90
5.10
3.90
4.10
4.30
1.50
1.70
1.90
6.15 BSC
5.70
5.90
6.10
3.90
4.15
4.40
1.27 BSC
0.45
0.55
0.65
−−−
−−−
12 _
0.51
−−−
−−−
0.56
−−−
−−−
0.48
0.61
0.71
3.25
3.50
3.75
1.80
2.00
2.20
ALTERNATE
CONSTRUCTION
DETAIL B
M
XXXXXX= Specific Device Code
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
SEATING
PLANE
NOTE 6
DIM
A
A1
b
b1
c
D
D1
D2
D3
E
E1
E2
e
G
h
K
K1
L
M
N
8
5
8X
SOLDERING FOOTPRINT*
E2
4.56
0.75
b
K1
BOTTOM VIEW
2X
0.10
C A B
0.05
C
2X
2.08
8X
0.56
NOTE 3
4.84
4X
1.40
2.30
6.59
3.70
0.70
4X
1.00
1.27
PITCH
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON50417E
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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