NVMFS4C302N
Power MOSFET
30 V, 1.15 mW, 241 A, Single N−Channel
Logic Level, SO−8FL
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFS4C302NWF − Wettable Flanks Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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V(BR)DSS
RDS(on) MAX
ID MAX
1.15 mW @ 10 V
30 V
241 A
1.7 mW @ 4.5 V
D (5,6)
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Drain−to−Source Voltage
Symbol
Value
Unit
VDSS
30
V
VGS
"20
V
TC = 25°C
ID
241
A
Power Dissipation
RqJC (Notes 1, 2)
TC = 25°C
PD
115
W
Continuous Drain Current RqJA (Notes 1, 2,
3)
TA = 25°C
ID
43
A
Gate−to−Source Voltage
Continuous Drain Current RqJC (Notes 1, 2,
3)
G (4)
S (1,2,3)
N−CHANNEL MOSFET
Steady
State
Steady
State
Power Dissipation
RqJA (Notes 1, 2)
Pulsed Drain Current
D
1
TA = 25°C
TA = 25°C, tp = 10 ms
PD
3.75
W
IDM
900
A
TJ, Tstg
−55 to
175
°C
IS
153
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 61 A)
EAS
186
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Operating Junction and Storage Temperature
Source Current (Body Diode)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Symbol
Value
Unit
Junction−to−Case − Steady State (Note 2)
RqJC
1.3
°C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
40
Parameter
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2016
SO−8 FLAT LEAD
CASE 488AA
STYLE 1
1
S
S
S
G
D
4C02xx
AYWZZ
D
D
4C02N = Specific Device Code for
NVMFS4C302N
4C02WF= Specific Device Code of
NVMFS4C302NWF
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceabililty
ORDERING INFORMATION
Package
Shipping†
NVMFS4C302NT1G
SO−8 FL
(Pb−Free)
1500 /
Tape & Reel
NVMFS4C302NWFT1G
SO−8 FL
(Pb−Free)
1500 /
Tape & Reel
Device
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
December, 2017 − Rev. 0
MARKING
DIAGRAM
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NVMFS4C302N/D
NVMFS4C302N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
24
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25 °C
1.0
TJ = 125°C
100
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 250 mA
100
mA
nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
VGS(TH)/TJ
RDS(on)
1.3
2.2
5.8
V
mV/°C
VGS = 10 V
ID = 30 A
0.95
1.15
VGS = 4.5 V
ID = 30 A
1.35
1.7
mW
Forward Transconductance
gFS
VDS = 3 V, ID = 30 A
135
S
Gate Resistance
RG
TA = 25 °C
1.0
W
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
70
Total Gate Charge
QG(TOT)
37
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
5780
VGS = 0 V, f = 1 MHz, VDS = 15 V
2320
pF
9.0
VGS = 4.5 V, VDS = 15 V; ID = 30 A
nC
16
7.0
QG(TOT)
VGS = 10 V, VDS = 15 V,
ID = 30 A
82
nC
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
13
tr
td(OFF)
VGS = 10 V, VDS = 15 V, ID = 15 A,
RG = 3.0 W
tf
18
ns
54
9.0
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.75
TJ = 125°C
0.6
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 10 A
1.1
V
56
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
QRR
29
ns
27
69
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS4C302N
TYPICAL CHARACTERISTICS
450
10 V
6V
4.5 V
400
350
300
3.7 V
250
3.5 V
200
3.3 V
150
3.1 V
2.9 V
100
2.7 V
2.5 V
50
1
2
1.5
2.5
250
200
150
TJ = 125°C
100
TJ = 25°C
4.0
Figure 2. Transfer Characteristics
TJ = 25°C
ID = 30 A
1.75
1.55
1.35
1.15
0.95
0.75
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
4.5
2.35
TJ = 25°C
2.15
1.95
1.75
VGS = 4.5 V
1.55
1.35
1.15
VGS = 10 V
0.95
0.75
0
50
100
150
200
250
300
350
400 450
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. VGS
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1000000
1.8
VGS = 0 V
VGS = 10 V
ID = 30 A
TJ = 175°C
100000
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
3.5
Figure 1. On−Region Characteristics
1.95
1.6
3.0
VGS, GATE−TO−SOURCE VOLTAGE (V)
2.15
1.7
TJ = −55°C
2.5
2.0
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
2.35
3
300
0
1.5
3
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
0.5
350
50
0
0
VDS = 3 V
400
4.0 V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
450
TJ = 25°C
1.5
1.4
1.3
1.2
1.1
1.0
TJ = 150°C
10000
TJ = 125°C
TJ = 100°C
1000
TJ = 85°C
100
0.9
0.8
0.7
−50 −25
10
0
25
50
75
100
125
150
175
0
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
30
NVMFS4C302N
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
10000
C, CAPACITANCE (pF)
Ciss
Coss
1000
Crss
100
VGS = 0 V
TJ = 25°C
f = 1 MHz
10
0
5
10
15
20
25
QT
9
8
7
6
5
4
Qgd
Qgs
3
VDS = 15 V
ID = 30 A
TJ = 25°C
2
1
0
0
30
20
10
30
40
50
60
70
80
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
90
1000
1000
VGS = 0 V
IS, SOURCE CURRENT (A)
td(off)
VGS = 10 V
VDD = 15 V
ID = 15 A
tf
100
tr
td(on)
10
1
1
10
100
10
TJ = 150°C
1
0.1
0.2
100
TJ = 175°C
TJ = 25°C
0.3
0.4
0.5
0.6
TJ = −55°C
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
ID, DRAIN CURRENT (A)
t, TIME (ns)
11
10
100
100 ms
10
1
VGS < 10 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
0.1
0.01
1 ms
10 ms
dc
0.1
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
100
1.1
NVMFS4C302N
TYPICAL CHARACTERISTICS
100
RqJA Steady State = 40°C/W
R(t) (°C/W)
Duty Cycle = 50%
10 20%
10%
5%
1 2%
1%
0.1
0.01
Single Pulse
0.001
0.00001
0.0001
0.001
0.1
0.01
1
10
PULSE TIME (sec)
Figure 12. Thermal Response
1000
IPEAK, DRAIN CURRENT (A)
0.000001
TJ = 25°C
100
TJ = 100°C
10
1
1.0E−6
10E−6
100E−6
1.0E−3
10E−3
TIME IN AVALANCHE (S)
Figure 13. Maximum Drain Current vs. Time in
Avalanche
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5
100
1000
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE N
1
DATE 25 JUN 2018
SCALE 2:1
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
A
2
B
D1
2X
0.20 C
4X
E1
2
q
E
c
1
2
3
A1
4
TOP VIEW
C
DETAIL A
0.10 C
SEATING
PLANE
A
0.10 C
SIDE VIEW
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.00
5.15
5.30
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.30
6.15
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.575
0.71
1.20
1.35
1.50
0.51
0.575
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
GENERIC
MARKING DIAGRAM*
DETAIL A
1
0.10
b
C A B
0.05
c
8X
XXXXXX
AYWZZ
e/2
e
L
1
4
K
RECOMMENDED
SOLDERING FOOTPRINT*
E2
PIN 5
(EXPOSED PAD)
L1
M
2X
0.495
4.560
2X
1.530
G
D2
2X
BOTTOM VIEW
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
0.475
3.200
4.530
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
1.330
STYLE 2:
2X
PIN 1. ANODE
0.905
2. ANODE
3. ANODE
4. NO CONNECT
0.965
5. CATHODE
1
4X
1.000
4X 0.750
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14036D
DFN5 5x6, 1.27P (SO−8FL)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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