NVMFS5C410NLWFT3G

NVMFS5C410NL MOSFET – Power, Single N-Channel 40 V, 0.82 mW, 330 A Features • • • • • • Small Footprint (5x6 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses NVMFS5C410NLWF − Wettable Flank Option for Enhanced Optical Inspection AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com V(BR)DSS RDS(ON) MAX ID MAX 0.82 mW @ 10 V 40 V 330 A 1.2 mW @ 4.5 V D (5,6) MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 40 V Gate−to−Source Voltage VGS ±20 V ID 330 A Parameter Continuous Drain Current RqJC (Notes 1, 3) TC = 25°C Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1, 2, 3) Steady State TC = 100°C TC = 25°C TA = 25°C Power Dissipation RqJA (Notes 1 & 2) PD Steady State W 167 83 ID TA = 100°C 35 1 3.8 IDM 900 A TJ, Tstg −55 to +175 °C IS 169 A Single Pulse Drain−to−Source Avalanche Energy (IL(pk) = 29 A) EAS 706 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Pulsed Drain Current TA = 100°C TA = 25°C, tp = 10 ms Operating Junction and Storage Temperature Source Current (Body Diode) W 1.9 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter MARKING DIAGRAM A 50 PD TA = 25°C S (1,2,3) N−CHANNEL MOSFET 230 TC = 100°C G (4) Symbol Value Unit Junction−to−Case − Steady State RqJC 0.9 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 39 DFN5 (SO−8FL) CASE 488AA STYLE 1 D S S S G D XXXXXX AYWZZ D D XXXXXX = 5C410L XXXXXX = (NVMFS5C410NL) or XXXXXX = 410LWF XXXXXX = (NVMFS5C410NLWF) A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2016 July, 2019 − Rev. 7 1 Publication Order Number: NVMFS5C410NL/D NVMFS5C410NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 40 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 21.2 VGS = 0 V, VDS = 40 V mV/°C TJ = 25 °C 10 TJ = 125°C 250 IGSS VDS = 0 V, VGS = 20 V VGS(TH) VGS = VDS, ID = 250 mA 100 mA nA ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance Forward Transconductance RDS(on) 1.2 2.0 −5.75 VGS = 10 V ID = 50 A 0.65 0.82 VGS = 4.5 V ID = 50 A 0.95 1.2 gFS VDS = 15 V, ID = 50 A V mV/°C 190 mW S CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 8862 VGS = 0 V, f = 1 MHz, VDS = 25 V 4156 pF 116 Total Gate Charge QG(TOT) VGS = 4.5 V, VDS = 20 V; ID = 50 A 66 Total Gate Charge QG(TOT) VGS = 10 V, VDS = 20 V; ID = 50 A 143 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Plateau Voltage VGP 2.7 td(ON) 20 6.75 VGS = 4.5 V, VDS = 20 V; ID = 50 A nC 21.4 22 V SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(OFF) VGS = 4.5 V, VDS = 20 V, ID = 50 A, RG = 1.0 W tf 130 ns 66 177 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 50 A TJ = 25°C 0.73 TJ = 125°C 0.6 tRR ta tb 1.2 V 79.5 VGS = 0 V, dIS/dt = 100 A/ms, IS = 50 A QRR 39 ns 40.5 126 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NVMFS5C410NL TYPICAL CHARACTERISTICS 200 ID, DRAIN CURRENT (A) 140 120 2.8 V 100 80 60 40 140 120 100 80 TJ = 25°C 60 40 TJ = 125°C 20 0 0.5 1.0 1.5 2.0 0 3.0 2.5 0 1.0 1.5 TJ = −55°C 2.0 2.5 3.0 3.5 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.0013 4.0 0.0012 0.0012 0.0011 TJ = 25°C VGS = 4.5 V 0.0010 TJ = 25°C ID = 50 A 0.0011 0.0009 0.0010 0.0008 0.0009 0.0007 0.0008 0.0006 VGS = 10 V 0.0006 0.0007 0.0005 3 4 5 6 7 8 9 VGS, GATE VOLTAGE (V) 10 0.0004 10 20 30 40 50 60 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.9 1M 1.7 VGS = 10 V ID = 40 A TJ = 150°C 100k IDSS, LEAKAGE (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE 0.5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (A) 160 3.0 V 160 20 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 180 10 V to 3.2 V 180 1.5 1.3 1.1 TJ = 125°C 10k TJ = 85°C 1k 100 0.9 0.7 −50 −25 0 25 50 75 100 125 150 175 10 5 10 15 20 25 30 35 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 40 NVMFS5C410NL 11k CISS C, CAPACITANCE (pF) 9k 8k COSS 7k VGS = 0 V TJ = 25°C f = 1 MHz 6k 5k 4k 3k 2k CRSS 5 0 15 10 25 20 30 40 15 4 QGD QGS 2 0 0 20 10 VDS = 20 V TJ = 25°C ID = 50 A 60 40 80 120 100 5 140 0 Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge td(off) tf tr 46 td(on) 10 VGS = 4.5 V VDD = 20 V ID = 50 A 1 41 36 31 26 TJ = 125°C 21 16 11 TJ = 150°C TJ = 25°C 6 10 1 100 0.3 0.4 0.5 0.6 0.7 TJ = −55°C 0.8 0.9 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1000 TC = 25°C VGS ≤ 10 V 0.01 ms 0.1 ms 100 100 IDS (A) 1 ms dc TJ(initial) = 25°C IPEAK (A) 1000 20 6 QG, TOTAL GATE CHARGE (nC) 100 1 25 8 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 10,00 t, TIME (ns) 35 30 QT IS, SOURCE CURRENT (A) 1k 0 VGS, GATE−TO−SOURCE VOLTAGE (V) 10 10k VDS, DRAIN−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS 10 ms TJ(initial) = 100°C 10 10 RDS(on) Limit Thermal Limit Package Limit 1 0.1 1 10 1 100 1E−04 1E−03 VDS (V) TIME IN AVALANCHE (s) Figure 11. Safe Operating Area Figure 12. IPEAK vs. Time in Avalanche www.onsemi.com 4 1E−02 NVMFS5C410NL 100 RqJA(t) (°C/W) 50% Duty Cycle 10 20% 10% 5% 1 2% 1% NVMFS5C410NL 650 mm2, 2 oz., Cu Single Layer Pad 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE TIME (sec) Figure 13. Thermal Characteristics DEVICE ORDERING INFORMATION Device Marking Package Shipping† NVMFS5C410NLT1G 5C410L DFN5 (Pb−Free) 1500 / Tape & Reel NVMFS5C410NLWFT1G 410LWF DFN5 (Pb−Free, Wettable Flanks) 1500 / Tape & Reel NVMFS5C410NLT3G 5C410L DFN5 (Pb−Free) 5000 / Tape & Reel NVMFS5C410NLWFT3G 410LWF DFN5 (Pb−Free, Wettable Flanks) 5000 / Tape & Reel NVMFS5C410NLAFT1G 5C410L DFN5 (Pb−Free) 1500 / Tape & Reel NVMFS5C410NLWFAFT1G 410LWF DFN5 (Pb−Free, Wettable Flanks) 1500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN5 5x6, 1.27P (SO−8FL) CASE 488AA ISSUE N 1 DATE 25 JUN 2018 SCALE 2:1 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 0.20 C D A 2 B D1 2X 0.20 C 4X E1 2 q E c 1 2 3 A1 4 TOP VIEW C DETAIL A 0.10 C SEATING PLANE A 0.10 C SIDE VIEW MILLIMETERS MIN NOM MAX 0.90 1.00 1.10 0.00 −−− 0.05 0.33 0.41 0.51 0.23 0.28 0.33 5.00 5.15 5.30 4.70 4.90 5.10 3.80 4.00 4.20 6.00 6.30 6.15 5.70 5.90 6.10 3.45 3.65 3.85 1.27 BSC 0.51 0.575 0.71 1.20 1.35 1.50 0.51 0.575 0.71 0.125 REF 3.00 3.40 3.80 0_ −−− 12 _ DIM A A1 b c D D1 D2 E E1 E2 e G K L L1 M q GENERIC MARKING DIAGRAM* DETAIL A 1 0.10 b C A B 0.05 c 8X XXXXXX AYWZZ e/2 e L 1 4 K RECOMMENDED SOLDERING FOOTPRINT* E2 PIN 5 (EXPOSED PAD) L1 M 2X 0.495 4.560 2X 1.530 G D2 2X BOTTOM VIEW XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. 0.475 3.200 4.530 STYLE 1: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 1.330 STYLE 2: 2X PIN 1. ANODE 0.905 2. ANODE 3. ANODE 4. NO CONNECT 0.965 5. CATHODE 1 4X 1.000 4X 0.750 1.270 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON14036D DFN5 5x6, 1.27P (SO−8FL) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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