NVMFS5C430NLT3G

NVMFS5C430NL MOSFET – Power, Single N-Channel 40 V, 1.4 mW, 200 A Features • • • • • • Small Footprint (5x6 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses NVMFS5C430NLWF − Wettable Flank Option for Enhanced Optical Inspection AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant www.onsemi.com V(BR)DSS RDS(ON) MAX 1.4 mW @ 10 V 40 V D (5,6) Symbol Value Unit Drain−to−Source Voltage VDSS 40 V Gate−to−Source Voltage VGS ±20 V ID 200 A Continuous Drain Current RqJC (Notes 1, 3) TC = 25°C Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1, 2, 3) Steady State TC = 100°C TC = 25°C TC = 100°C TA = 25°C Power Dissipation RqJA (Notes 1 & 2) Pulsed Drain Current Steady State TA = 25°C, tp = 10 ms Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (IL(pk) = 15 A) Single Pulse Drain−to−Source Voltage (tp = 10 ms) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) MARKING DIAGRAM A 38 PD W 3.8 1.9 IDM 900 A TJ, Tstg −55 to + 175 °C IS 120 A EAS 493 mJ VDSM 48 V TL 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter N−CHANNEL MOSFET 27 TA = 100°C Operating Junction and Storage Temperature W 110 53 ID TA = 100°C TA = 25°C G (4) S (1,2,3) 140 PD 200 A 2.2 mW @ 4.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter ID MAX Symbol Value Unit Junction−to−Case − Steady State RqJC 1.4 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 40 1 DFN5 (SO−8FL) CASE 488AA STYLE 1 D S S S G D XXXXXX AYWZZ D D XXXXXX = 5C430L XXXXXX = (NVMFS5C430NL) or XXXXXX = 430LWF XXXXXX = (NVMFS5C430NLWF) A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability ORDERING INFORMATION See detailed ordering, marking and shipping information on page 5 of this data sheet. 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2016 July, 2019 − Rev. 3 1 Publication Order Number: NVMFS5C430NL/D NVMFS5C430NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 40 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 1.3 VGS = 0 V, VDS = 40 V mV/°C TJ = 25 °C 10 TJ = 125°C 250 IGSS VDS = 0 V, VGS = 20 V VGS(TH) VGS = VDS, ID = 250 mA 100 mA nA ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance Forward Transconductance RDS(on) 1.2 2.0 −5.6 VGS = 4.5 V ID = 50 A 1.7 2.2 VGS = 10 V ID = 50 A 1.2 1.4 gFS VDS =15 V, ID = 50 A V mV/°C 180 mW S CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 4300 VGS = 0 V, f = 1 MHz, VDS = 20 V 1900 pF 72 Total Gate Charge QG(TOT) VGS = 4.5 V, VDS = 20 V; ID = 50 A 32 Total Gate Charge QG(TOT) VGS = 10 V, VDS = 20 V; ID = 50 A 70 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Plateau Voltage VGP 2.9 td(ON) 15 7.0 VGS = 4.5 V, VDS = 20 V; ID = 50 A nC 12 9.0 V SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(OFF) VGS = 4.5 V, VDS = 20 V, ID = 50 A, RG = 1 W tf 140 ns 31 9 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 50 A TJ = 25°C 0.81 TJ = 125°C 0.68 tRR ta tb 1.2 V 61 VGS = 0 V, dIs/dt = 100 A/ms, IS = 50 A QRR 29 ns 32 80 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NVMFS5C430NL TYPICAL CHARACTERISTICS 280 280 3.2 V 160 120 3.0 V 80 2.8 V 40 2.6 V 160 120 TJ = 25°C 80 40 TJ = −55°C TJ = 125°C 1 1.5 2 2.5 3 3.5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics TJ = 25°C ID = 50 A 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 2.0 200 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 5.0 0.0 VDS = 5 V 240 ID, DRAIN CURRENT (A) 200 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) 3.4 V 3.6 V to 10 V 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 VGS, GATE VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) ID, DRAIN CURRENT (A) 240 3.0 4 TJ = 25°C 2.5 2.0 VGS = 4.5 V 1.5 VGS = 10 V 1.0 0.5 0 20 60 100 140 180 220 260 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 100000 RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE 1.9 VGS = 10 V ID = 50 A TJ = 175°C IDSS, LEAKAGE (nA) 1.7 1.5 1.3 1.1 10000 TJ = 125°C 1000 TJ = 85°C 100 0.9 0.7 −50 −25 0 25 50 75 100 125 150 175 10 0 10 20 30 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 40 NVMFS5C430NL TYPICAL CHARACTERISTICS VGS, GATE−TO−SOURCE VOLTAGE (V) 10000 C, CAPACITANCE (pF) CISS 10 COSS 1000 CRSS 100 10 VGS = 0 V TJ = 25°C f = 1 MHz 0 10 20 30 40 QT 8 6 QGD QGS 4 VDS = 20 V TJ = 25°C ID = 50 A 2 0 0 10 20 30 40 50 60 70 VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total Charge 100.0 1000.0 tr tf t, TIME (ns) 100.0 TJ = 125°C td(on) IS, (A) td(off) 10.0 TJ = 25°C 10.0 VGS = 4.5 V VDD = 20 V ID = 50 A 1.0 1 10 TJ = −55°C 1.0 100 1 0.1 0.1 0.6 0.7 0.8 0.9 1.0 Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 100 100 TJ = 25°C TC = 25°C VGS ≤ 10 V Single Pulse IPEAK, (A) 10 0.5 VSD, SOURCE−TO−DRAIN VOLTAGE (V) 1000 ID, DRAIN CURRENT (A) 0.4 RG, GATE RESISTANCE (W) 500 ms TJ = 100°C 10 1 ms RDS(on) Limit Thermal Limit Package Limit 1 10 ms 10 1 100 1E−4 1E−3 10E−2 VDS (V) TIME IN AVALANCHE (s) Figure 11. Safe Operating Area Figure 12. IPEAK vs. Time in Avalanche www.onsemi.com 4 NVMFS5C430NL TYPICAL CHARACTERISTICS 100 RqJA (°C/W) 50% Duty Cycle 10 20% 10% 5% 1 2% 1% 0.1 0.01 0.000001 Single Pulse 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE TIME (sec) Figure 13. Thermal Characteristics DEVICE ORDERING INFORMATION Device Marking Package Shipping† NVMFS5C430NLT1G 5C430L DFN5 (Pb−Free) 1500 / Tape & Reel NVMFS5C430NLWFT1G 430LWF DFN5 (Pb−Free, Wettable Flanks) 1500 / Tape & Reel NVMFS5C430NLT3G 5C430L DFN5 (Pb−Free) 5000 / Tape & Reel NVMFS5C430NLWFT3G 430LWF DFN5 (Pb−Free, Wettable Flanks) 5000 / Tape & Reel NVMFS5C430NLAFT1G 5C430L DFN5 (Pb−Free) 1500 / Tape & Reel NVMFS5C430NLWFAFT1G 430LWF DFN5 (Pb−Free, Wettable Flanks) 1500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN5 5x6, 1.27P (SO−8FL) CASE 488AA ISSUE N 1 DATE 25 JUN 2018 SCALE 2:1 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 0.20 C D A 2 B D1 2X 0.20 C 4X E1 2 q E c 1 2 3 A1 4 TOP VIEW C DETAIL A 0.10 C SEATING PLANE A 0.10 C SIDE VIEW MILLIMETERS MIN NOM MAX 0.90 1.00 1.10 0.00 −−− 0.05 0.33 0.41 0.51 0.23 0.28 0.33 5.00 5.15 5.30 4.70 4.90 5.10 3.80 4.00 4.20 6.00 6.30 6.15 5.70 5.90 6.10 3.45 3.65 3.85 1.27 BSC 0.51 0.575 0.71 1.20 1.35 1.50 0.51 0.575 0.71 0.125 REF 3.00 3.40 3.80 0_ −−− 12 _ DIM A A1 b c D D1 D2 E E1 E2 e G K L L1 M q GENERIC MARKING DIAGRAM* DETAIL A 1 0.10 b C A B 0.05 c 8X XXXXXX AYWZZ e/2 e L 1 4 K RECOMMENDED SOLDERING FOOTPRINT* E2 PIN 5 (EXPOSED PAD) L1 M 2X 0.495 4.560 2X 1.530 G D2 2X BOTTOM VIEW XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. 0.475 3.200 4.530 STYLE 1: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 1.330 STYLE 2: 2X PIN 1. ANODE 0.905 2. ANODE 3. ANODE 4. NO CONNECT 0.965 5. CATHODE 1 4X 1.000 4X 0.750 1.270 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON14036D DFN5 5x6, 1.27P (SO−8FL) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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