DATA SHEET
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MOSFET – Power, Single
N-Channel
V(BR)DSS
RDS(ON) MAX
7.3 m @ 10 V
40 V
D (5,6)
NVMFS5C466NL
Features
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFS5C466NLWF − Wettable Flank Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
40
V
Gate−to−Source Voltage
VGS
±20
V
ID
52
A
Parameter
Continuous Drain
Current RJC
(Notes 1, 3)
TC = 25°C
Power Dissipation
RJC (Note 1)
Continuous Drain
Current RJA
(Notes 1, 2, 3)
Steady
State
TC = 100°C
TC = 25°C
Power Dissipation
RJA (Notes 1 & 2)
Pulsed Drain Current
37
PD
TC = 100°C
TA = 25°C
Steady
State
ID
PD
A
16
W
3.5
1.75
IDM
238.6
A
TJ, Tstg
−55 to
+ 175
°C
IS
31.25
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 2.93 A)
EAS
65
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
TA = 25°C, tp = 10 s
Operating Junction and Storage Temperature
Source Current (Body Diode)
S (1,2,3)
N−CHANNEL MOSFET
1
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
DFNW5 5x6
(FULL−CUT SO8FL WF)
CASE 507BA
MARKING DIAGRAM
11
TA = 100°C
G (4)
W
37
19
TA = 100°C
TA = 25°C
52 A
12 m @ 4.5 V
40 V, 7.3 mW, 52 A
•
•
•
•
ID MAX
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
D
S
S
S
G
D
XXXXXX
AYWZZ
D
D
XXXXXX = 5C466NL
XXXXXX = (NVMFS5C466NL) or
XXXXXX = 466LWF
XXXXXX = (NVMFS5C466NLWF)
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction−to−Case − Steady State
RJC
4.0
°C/W
Junction−to−Ambient − Steady State (Note 2)
RJA
43
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
© Semiconductor Components Industries, LLC, 2017
April, 2022 − Rev.1
1
Publication Order Number:
NVMFS5C466NL/D
NVMFS5C466NL
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Symbol
Test Condition
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 A
40
−
−
V
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
−
25
−
TJ = 25 °C
−
−
10
TJ = 125°C
−
−
250
Parameter
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
VGS = 0 V,
VDS = 40 V
mV/°C
A
IGSS
VDS = 0 V, VGS = 20 V
−
−
100
nA
VGS(TH)
VGS = VDS, ID = 30 A
1.2
−
2.2
V
−
−4.9
−
mV/°C
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
VGS = 4.5 V
ID = 10 A
−
9.7
12
m
Drain−to−Source On Resistance
RDS(on)
VGS = 10 V
ID = 10 A
−
6.1
7.3
m
−
33
−
S
−
860
−
−
360
−
−
15
−
Forward Transconductance
gFS
VDS =15 V, ID = 10 A
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VGS = 0 V, f = 1 MHz, VDS = 25 V
pF
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 32 V; ID = 10 A
−
7
−
nC
Total Gate Charge
QG(TOT)
VGS = 10 V, VDS = 32 V; ID = 10 A
−
16
−
nC
Threshold Gate Charge
QG(TH)
−
1.8
−
Gate−to−Source Charge
QGS
−
3.3
−
Gate−to−Drain Charge
QGD
−
2.5
−
Plateau Voltage
VGP
−
3.4
−
td(ON)
−
8
−
−
24
−
−
29
−
−
6
−
TJ = 25°C
−
0.84
1.2
TJ = 125°C
−
0.71
−
−
24
−
−
11
−
−
12
−
−
11
v
VGS = 10 V, VDS = 32 V; ID = 10 A
nC
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 10 V, VDS = 32 V,
ID = 10 A, RG = 1
tf
ns
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 10 A
VGS = 0 V, dIS/dt = 100 A/s,
IS = 10 A
QRR
V
ns
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 s, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS5C466NL
TYPICAL CHARACTERISTICS
100
VGS = 10 to 5 V
ID, DRAIN CURRENT (A)
50
3.8 V
40
3.6 V
30
3.4 V
20
3.2 V
10
0
0.5
1.0
2.0
1.5
70
60
50
40
30
TJ = 25°C
20
2.5
0
3.0
0
2
1
TJ = −55°C
3
4
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (m)
Figure 1. On−Region Characteristics
20
15
10
5
4
5
6
7
8
9
10
12
TJ = 25°C
11
6
5
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 25 A
TJ = 25°C
3
TJ = 125°C
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
25
0
80
10
VGS = 4.5 V
10
9
8
7
VGS = 10 V
6
5
4
10
15
20
25
30
40
35
45
50
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10K
1.8
1.6
ID = 10 A
VGS = 10 V
TJ = 150°C
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (m)
0
VDS = 10 V
90
4.5 V
60
ID, DRAIN CURRENT (A)
70
1.4
1.2
1.0
1K
TJ = 125°C
100
TJ = 85°C
0.8
0.6
−50 −25
0
25
50
75
100
125
150
10
175
5
10
15
20
25
30
35
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
40
NVMFS5C466NL
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
5K
C, CAPACITANCE (pF)
Ciss
500
Coss
50
TJ = 25°C
VGS = 0 V
f = 1 MHz
5
0
5
Crss
10
15
20
25
30
35
40
10
9
8
7
6
5
Qgs
4
3
VDS = 32 V
ID = 10 A
TJ = 25°C
2
1
0
0
2
14
VGS = 10 V
VDS = 32 V
1
1
10
16
VGS = 0 V
IS, SOURCE CURRENT (A)
t, TIME (ns)
td(on)
tf
TJ = 125°C
0.3
0.4
0.5
TJ =
−55°C
TJ = 25°C
0.6
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE ()
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
Single Pulse
VGS ≤ 10 V
TC = 25°C
TJ(initial) = 25°C
10
IPEAK (A)
ID, DRAIN CURRENT (A)
12
10
Figure 8. Gate−to−Source vs. Total Charge
tr
100
8
Figure 7. Capacitance Variation
td(off)
1000
6
Qg, TOTAL GATE CHARGE (nC)
100
1
4
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
10
10
Qgd
10
TJ(initial) = 100°C
1
1
0.1
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
10
10 s
0.5 ms
1 ms
10 ms
100
1000
0.1
0.00001
0.0001
0.001
0.01
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NVMFS5C466NL
TYPICAL CHARACTERISTICS
100
50% Duty Cycle
R(t) (°C/W)
10
1
20%
10%
5%
2%
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Device
Marking
Package
Shipping†
NVMFS5C466NLT1G
5C466L
DFN5 5x6, 1.27P
(SO−8FL)
(Pb−Free)
1500 / Tape & Reel
NVMFS5C466NLWFT1G
466LWF
DFNW5, 5x6
(FULL−CUT SO8FL WF)
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE N
1
DATE 25 JUN 2018
SCALE 2:1
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
2
A
B
D1
2X
0.20 C
4X
E1
2
1
2
3
q
E
c
A1
4
TOP VIEW
C
DETAIL A
0.10 C
SEATING
PLANE
A
0.10 C
SIDE VIEW
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.00
5.15
5.30
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.30
6.15
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.575
0.71
1.20
1.35
1.50
0.51
0.575
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
GENERIC
MARKING DIAGRAM*
DETAIL A
1
0.10
b
C A B
0.05
c
8X
XXXXXX
AYWZZ
e/2
e
L
1
4
K
PIN 5
(EXPOSED PAD)
RECOMMENDED
SOLDERING FOOTPRINT*
E2
L1
M
2X
0.495
4.560
2X
1.530
G
D2
BOTTOM VIEW
2X
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
0.475
3.200
4.530
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
1.330
STYLE 2:
2X
PIN 1. ANODE
0.905
2. ANODE
3. ANODE
4. NO CONNECT
0.965
5. CATHODE
1
4X
1.000
4X 0.750
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14036D
DFN5 5x6, 1.27P (SO−8FL)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFNW5 5x6 (FULL−CUT SO8FL WF)
CASE 507BA
ISSUE A
DATE 03 FEB 2021
q
q
GENERIC
MARKING DIAGRAM*
1
XXXXXX
AYWZZ
XXXXXX
A
Y
W
ZZ
= Specific Device Code *This information is generic. Please refer to
= Assembly Location
device data sheet for actual part marking.
= Year
Pb−Free indicator, “G” or microdot “ G”,
= Work Week
may or may not be present. Some products
= Lot Traceability
may not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON26450H
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DFNW5 5x6 (FULL−CUT SO8FL WF)
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
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onsemi,
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