DATA SHEET
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MOSFET - Power, Single
N-Channel, DFN5/DFNW5
60 V, 4.6 mW, 92 A
V(BR)DSS
RDS(ON) MAX
ID MAX
60 V
4.6 mW @ 10 V
92 A
NVMFS5C645N
D (5)
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFS5C645NWF − Wettable Flank Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
G (4)
S (1,2,3)
N−CHANNEL MOSFET
MARKING
DIAGRAM
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
V
Gate−to−Source Voltage
VGS
±20
V
ID
92
A
Parameter
Continuous Drain
Current RqJC
(Notes 1, 3)
TC = 25°C
Power Dissipation
RqJC (Note 1)
Continuous Drain
Current RqJA
(Notes 1, 2, 3)
Steady
State
TC = 100°C
TC = 25°C
Pulsed Drain Current
PD
TC = 100°C
TA = 25°C
Power Dissipation
RqJA (Notes 1 & 2)
65
Steady
State
40
ID
TA = 100°C
TA = 25°C
W
79
A
20
14
PD
TA = 100°C
W
3.7
820
A
TJ, Tstg
−55 to
+175
°C
IS
100
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 5 A)
EAS
185
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Operating Junction and Storage Temperature
Source Current (Body Diode)
DFNW5
CASE 507BA
D
S
S
S
G
D
XXXXXX
AYWZZ
D
D
XXXXXX = 5C645N
XXXXXX = (NVMFS5C645N) or
XXXXXX = 645NWF
XXXXXX = (NVMFS5C645NWF)
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
1.8
IDM
TA = 25°C, tp = 10 ms
1
DFN5
CASE 488AA
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction−to−Case − Steady State
RqJC
1.9
°C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
41
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2015
September, 2021 − Rev. 1
1
Publication Order Number:
NVMFS5C645N/D
NVMFS5C645N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
60
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
22.4
VGS = 0 V,
VDS = 48 V
mV/°C
TJ = 25 °C
10
TJ = 125°C
250
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 250 mA
100
mA
nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
2.0
4.0
−7.3
VGS = 10 V
ID = 50 A
3.9
V
mV/°C
4.6
mW
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
1500
VGS = 0 V, f = 1 MHz, VDS = 25 V
1100
VGS = 10 V, VDS = 48 V; ID = 25 A
20.4
CRSS
pF
13
Total Gate Charge
QG(TOT)
Threshold Gate Charge
QG(TH)
4.5
Gate−to−Source Charge
QGS
7.8
Gate−to−Drain Charge
QGD
Plateau Voltage
VGP
5.1
td(ON)
13.2
VGS = 10 V, VDS = 48 V; ID = 25 A
nC
2.4
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 10 V, VDS = 48 V,
ID = 25 A, RG = 2.5 W
tf
36.3
ns
27
5.8
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.88
TJ = 125°C
0.76
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 50 A
1.2
V
44
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 50 A
QRR
23
ns
21
40
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS5C645N
TYPICAL CHARACTERISTICS
150
10 V to
4.5 V
VDS = 10 V
ID, DRAIN CURRENT (A)
125
VGS = 6.0 V
100
50
4.5 V
25
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
5.0 V
75
0
0.5
1.0
1.5
2.0
2.5
3.0
100
75
50
TJ = 25°C
25
TJ = 125°C
0
2
4
3
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
13
TJ = 25°C
ID = 50 A
12
11
10
9
8
7
6
5
4
5
6
7
9
8
10
VGS, GATE VOLTAGE (V)
6
5
VGS, GATE−TO−SOURCE VOLTAGE (V)
45
40
TJ = 25°C
VGS = 4.5 V
35
30
25
20
15
10
VGS = 10 V
5
0
5
10
15
20
25
30
35
40
45
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.0
100,000
VGS = 10 V
1.8 ID = 50 A
IDSS, LEAKAGE (nA)
1.6
1.4
1.2
1.0
TJ = 150°C
10,000
TJ = 125°C
1000
TJ = 85°C
100
0.8
0.6
−50 −25
0
25
50
75
100
125
150
50
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
1
TJ = −55°C
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
14
4
125
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
ID, DRAIN CURRENT (A)
150
175
10
5
15
25
35
45
55
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NVMFS5C645N
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
10,000
C, CAPACITANCE (pF)
CISS
1000
COSS
100
10
1
VGS = 0 V
TJ = 25°C
f = 1 MHz
0
CRSS
10
20
30
40
50
60
0
0
2
4
6
8
10
12
14
16
18
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
IS, SOURCE CURRENT (A)
t, TIME (ns)
VDS = 48 V
TJ = 25°C
ID = 50 A
2
20
100
td(on)
10
tf
VGS = 10 V
VDS = 48 V
ID = 50 A
1
10
10
TJ = 125°C
1
100
0.4
0.5
TJ = 25°C
0.6
0.7
TJ = −55°C
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
100
10 ms
TC = 25°C
Single Pulse
VGS ≤ 10 V
1
RDS(on) Limit
Thermal Limit
Package Limit
0.1
10
TJ(initial) = 25°C
IPEAK (A)
IDS (A)
4
Figure 7. Capacitance Variation
td(off)
0.1
QGD
QGS
6
QG, TOTAL GATE CHARGE (nC)
tr
10
8
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
100
1
10
1
10
1
0.5 ms
1 ms
10 ms
100
TJ(initial) = 100°C
1000
0.1
1E−04
1E−03
VDS (V)
TIME IN AVALANCHE (s)
Figure 11. Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
1E−02
NVMFS5C645N
TYPICAL CHARACTERISTICS
100
RqJA(t) (°C/W)
50% Duty Cycle
10
20%
10%
5%
1
2%
1%
NVMFS5C645N 650 mm2, 2 oz., Cu Single Layer Pad
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
Marking
Package
Shipping†
NVMFS5C645NT1G
5C645N
DFN5
(Pb−Free)
1500 / Tape & Reel
NVMFS5C645NWFT1G
645NWF
DFNW5
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE N
1
DATE 25 JUN 2018
SCALE 2:1
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
A
2
B
D1
2X
0.20 C
4X
E1
2
q
E
c
1
2
3
A1
4
TOP VIEW
C
DETAIL A
0.10 C
SEATING
PLANE
A
0.10 C
SIDE VIEW
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.00
5.15
5.30
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.30
6.15
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.575
0.71
1.20
1.35
1.50
0.51
0.575
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
GENERIC
MARKING DIAGRAM*
DETAIL A
1
0.10
b
C A B
0.05
c
8X
XXXXXX
AYWZZ
e/2
e
L
1
4
K
RECOMMENDED
SOLDERING FOOTPRINT*
E2
PIN 5
(EXPOSED PAD)
L1
M
2X
0.495
4.560
2X
1.530
G
D2
2X
BOTTOM VIEW
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
0.475
3.200
4.530
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
1.330
STYLE 2:
2X
PIN 1. ANODE
0.905
2. ANODE
3. ANODE
4. NO CONNECT
0.965
5. CATHODE
1
4X
1.000
4X 0.750
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14036D
DFN5 5x6, 1.27P (SO−8FL)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFNW5 5x6 (FULL−CUT SO8FL WF)
CASE 507BA
ISSUE A
DATE 03 FEB 2021
q
q
GENERIC
MARKING DIAGRAM*
1
XXXXXX
AYWZZ
XXXXXX
A
Y
W
ZZ
= Specific Device Code *This information is generic. Please refer to
= Assembly Location
device data sheet for actual part marking.
= Year
Pb−Free indicator, “G” or microdot “ G”,
= Work Week
may or may not be present. Some products
= Lot Traceability
may not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON26450H
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DFNW5 5x6 (FULL−CUT SO8FL WF)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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