NVMFS6H836NT1G

DATA SHEET www.onsemi.com MOSFET - Power, Single N-Channel 80 V, 6.7 mW, 80 A V(BR)DSS RDS(ON) MAX ID MAX 80 V 6.7 mW @ 10 V 80 A NVMFS6H836N D (5,6) Features • • • • • • Small Footprint (5x6 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses NVMFS6H836NWF − Wettable Flank Option for Enhanced Optical Inspection AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halide Free, and are RoHS Compliant MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RqJC (Notes 1, 3) Steady State Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1, 2, 3) Value Unit VDSS 80 V VGS ±20 V ID 74 A TC = 100°C TC = 25°C Power Dissipation RqJA (Notes 1, 2) TA = 25°C PD ID Operating Junction and Storage Temperature Range Source Current (Body Diode) PD W 3.7 1.8 IDM 432 A TJ, Tstg −55 to +175 °C IS 74 A Single Pulse Drain−to−Source Avalanche Energy (IL(pk) = 4.6 A) EAS 521 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter 1 DFN5 (SO−8FL) CASE 488AA STYLE 1 DFNW5 5x6 (FULL−CUT SO8FL WF) CASE 507BA Symbol Value Unit °C/W Junction−to−Case − Steady State RqJC 1.7 Junction−to−Ambient − Steady State (Note 2) RqJA 40.6 MARKING DIAGRAM D A 15 11 TA = 100°C TA = 25°C, tp = 10 ms W 89 44 TA = 100°C TA = 25°C S (1,2,3) N−CHANNEL MOSFET 53 TC = 100°C Steady State Pulsed Drain Current TC = 25°C Symbol G (4) S S S G D XXXXXX AYWZZ D D XXXXXX = 6H836N XXXXXX = (NVMFS6H836N) or XXXXXX = 836NWF XXXXXX = (NVMFS6H836NWF) A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2017 May, 2022 − Rev. 4 1 Publication Order Number: NVMFS6H836N/D NVMFS6H836N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage V(BR)DSS Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current 80 VGS = 0 V, ID = 250 mA V 39 VGS = 0 V, VDS = 80 V IGSS VDS = 0 V, VGS = 20 V VGS(TH) VGS = VDS, ID = 95 mA mV/°C TJ = 25°C 10 TJ = 125°C 100 100 mA nA ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Threshold Temperature Coefficient 2.0 VGS(TH)/TJ Drain−to−Source On Resistance Forward Transconductance RDS(on) gFS 4.0 −7.3 VGS = 10 V ID = 15 A VDS =15 V, ID = 25 A 5.6 V mV/°C 6.7 mW 97 S 1640 pF CHARGES, CAPACITANCES & GATE RESISTANCE VGS = 0 V, f = 1 MHz, VDS = 40 V Input Capacitance CISS Output Capacitance COSS 230 Reverse Transfer Capacitance CRSS 8.0 nC Total Gate Charge QG(TOT) VGS = 10 V, VDS = 40 V; ID = 25 A 25 Threshold Gate Charge QG(TH) VGS = 10 V, VDS = 40 V; ID = 25 A 5.2 Gate−to−Source Charge QGS 8.5 Gate−to−Drain Charge QGD 4.3 Plateau Voltage VGP 4.9 V 16 ns SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr VGS = 10 V, VDS = 64 V, ID = 25 A, RG = 2.5 W 45 td(OFF) 41 tf 34 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD tRR VGS = 0 V, IS = 15 A TJ = 25°C 0.8 TJ = 125°C 0.7 VGS = 0 V, dIS/dt = 100 A/ms, IS = 25 A 43 Charge Time ta Discharge Time tb 15 QRR 54 Reverse Recovery Charge 1.2 V ns 29 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NVMFS6H836N TYPICAL CHARACTERISTICS 200 ID, DRAIN CURRENT (A) 250 6V 150 100 5V 50 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) 300 VGS = 10 V 4V 0 1 2 4 3 5 7 6 8 TJ = 25°C 200 150 100 50 TJ = 125°C 0 1 2 3 TJ = −55°C 4 5 7 6 8 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 12 TJ = 25°C ID = 15 A 10 8 6 4 250 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) ID, DRAIN CURRENT (A) 300 5 6 7 8 9 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 9 10 14 15 12 TJ = 25°C 10 8 6 4 VGS = 10 V 5 6 7 8 9 10 11 12 13 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.5 100K IDSS, LEAKAGE (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE 1M VGS = 10 V ID = 15 A 2.0 1.5 1.0 0.5 TJ = 175°C TJ = 150°C 10K TJ = 125°C 1K TJ = 85°C 100 TJ = 25°C 10 0 −50 −25 0 25 50 75 100 125 150 175 1 5 15 25 35 45 55 65 75 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 NVMFS6H836N TYPICAL CHARACTERISTICS (continued) VGS, GATE−TO−SOURCE VOLTAGE (V) 10,000 C, CAPACITANCE (pF) CISS 1000 COSS 100 10 1 CRSS VGS = 0 V TJ = 25°C f = 1 MHz 10 0 20 30 40 50 60 70 80 10 9 8 7 QGS 6 QGD 5 4 3 VDS = 40 V TJ = 25°C ID = 25 A 2 1 0 0 5 10 20 15 25 VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total Charge 100 1000 td(off) tf tr 100 t, TIME (ns) IS, SOURCE CURRENT (A) VGS = 0 V td(on) 10 ID, DRAIN CURRENT(A) 1000 100 1 10 TJ = 125°C 0.3 0.4 0.5 0.6 TJ = 25°C TJ = −55°C 0.7 0.8 0.9 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 100 TC = 25°C Single Pulse VGS ≤ 10 V 0.5 ms 1 ms 10 ms TJ(initial) = 25°C 10 ms 10 1 0.1 1 0.1 100 IPEAK (A) 1 VGS = 10 V VDS = 64 V ID = 25 A 10 10 TJ(initial) = 100°C RDS(on) Limit Thermal Limit Package Limit 0.1 1 10 100 1000 1 1E−05 1E−04 1E−03 VDS, DRAIN−TO−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. IPEAK vs. Time in Avalanche www.onsemi.com 4 1E−02 NVMFS6H836N TYPICAL CHARACTERISTICS (continued) 100 Duty Cycle = 0.5 R(t) (°C/W) 10 0.2 0.1 0.05 1 0.02 0.01 0.1 0.01 Single Pulse 0.000001 0.00001 0.0001 0.001 0.1 0.01 1 10 100 1000 PULSE TIME (sec) Figure 13. Thermal Characteristics DEVICE ORDERING INFORMATION Marking Package Shipping† NVMFS6H836NT1G 6H836N DFN5 (Pb-Free, Halide Free) 1500 / Tape & Reel NVMFS6H836NT3G 6H836N DFN5 (Pb-Free, Halide Free) 5000 / Tape & Reel NVMFS6H836NWFT1G 836NWF DFNW5 (Pb-Free, Halide Free, Wettable Flanks) 1500 / Tape & Reel NVMFS6H836NWFT3G 836NWF DFNW5 (Pb-Free, Halide Free, Wettable Flanks) 5000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN5 5x6, 1.27P (SO−8FL) CASE 488AA ISSUE N 1 DATE 25 JUN 2018 SCALE 2:1 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 0.20 C D 2 A B D1 2X 0.20 C 4X E1 2 1 2 3 q E c A1 4 TOP VIEW C DETAIL A 0.10 C SEATING PLANE A 0.10 C SIDE VIEW MILLIMETERS MIN NOM MAX 0.90 1.00 1.10 0.00 −−− 0.05 0.33 0.41 0.51 0.23 0.28 0.33 5.00 5.15 5.30 4.70 4.90 5.10 3.80 4.00 4.20 6.00 6.30 6.15 5.70 5.90 6.10 3.45 3.65 3.85 1.27 BSC 0.51 0.575 0.71 1.20 1.35 1.50 0.51 0.575 0.71 0.125 REF 3.00 3.40 3.80 0_ −−− 12 _ DIM A A1 b c D D1 D2 E E1 E2 e G K L L1 M q GENERIC MARKING DIAGRAM* DETAIL A 1 0.10 b C A B 0.05 c 8X XXXXXX AYWZZ e/2 e L 1 4 K PIN 5 (EXPOSED PAD) RECOMMENDED SOLDERING FOOTPRINT* E2 L1 M 2X 0.495 4.560 2X 1.530 G D2 BOTTOM VIEW 2X XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. 0.475 3.200 4.530 STYLE 1: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 1.330 STYLE 2: 2X PIN 1. ANODE 0.905 2. ANODE 3. ANODE 4. NO CONNECT 0.965 5. CATHODE 1 4X 1.000 4X 0.750 1.270 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON14036D DFN5 5x6, 1.27P (SO−8FL) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFNW5 5x6 (FULL−CUT SO8FL WF) CASE 507BA ISSUE A DATE 03 FEB 2021 q q GENERIC MARKING DIAGRAM* 1 XXXXXX AYWZZ XXXXXX A Y W ZZ = Specific Device Code *This information is generic. Please refer to = Assembly Location device data sheet for actual part marking. = Year Pb−Free indicator, “G” or microdot “ G”, = Work Week may or may not be present. Some products = Lot Traceability may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON26450H Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DFNW5 5x6 (FULL−CUT SO8FL WF) PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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