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or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
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Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
NVMYS2D4N04C
MOSFET – Power, Single
N-Channel
40 V, 2.3 mW, 138 A
Features
•
•
•
•
•
•
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Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
LFPAK4 Package, Industry Standard
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
V(BR)DSS
RDS(ON) MAX
ID MAX
40 V
2.3 mW @ 10 V
138 A
D (5,8)
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
40
V
Gate−to−Source Voltage
VGS
±20
V
ID
138
A
Parameter
Continuous Drain
Current RqJC
(Notes 1, 3)
TC = 25°C
Power Dissipation
RqJC (Note 1)
Continuous Drain
Current RqJA
(Notes 1, 2, 3)
Steady
State
TC = 100°C
TC = 25°C
Power Dissipation
RqJA (Notes 1 & 2)
Steady
State
S (1,2,3)
78.1
PD
TC = 100°C
TA = 25°C
W
83
ID
A
30
3.9
IDM
829
A
TJ, Tstg
−55 to
+ 175
°C
IS
69
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 10 A)
EAS
220
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
TA = 100°C
TA = 25°C, tp = 10 ms
Operating Junction and Storage Temperature
Source Current (Body Diode)
W
1.9
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
MARKING
DIAGRAM
21
PD
Pulsed Drain Current
N−CHANNEL MOSFET
27
TA = 100°C
TA = 25°C
G (4)
Symbol
Value
Unit
Junction−to−Case − Steady State
RqJC
1.8
°C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
39
LFPAK4
CASE 760AB
2D4N04C
A
WL
Y
W
2D4N04
C
AWLYW
= Specific Device Code
= Assembly Location
=Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2018
July, 2019 − Rev. 0
1
Publication Order Number:
NVMYS2D4N04C/D
NVMYS2D4N04C
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
40
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
23
VGS = 0 V,
VDS = 40 V
mV/°C
TJ = 25 °C
10
TJ = 125°C
250
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 90 mA
100
mA
nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
2.5
3.5
−7.7
VGS = 10 V
gFS
ID = 50 A
VDS = 15 V, ID = 50 A
1.9
V
mV/°C
2.3
92
mW
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
2100
VGS = 0 V, f = 1 MHz, VDS = 25 V
1100
pF
40
Total Gate Charge
QG(TOT)
VGS = 10 V, VDS = 20 V; ID = 50 A
Threshold Gate Charge
QG(TH)
6.6
Gate−to−Source Charge
QGS
11
Gate−to−Drain Charge
QGD
Plateau Voltage
VGP
4.7
td(ON)
11
VGS = 10 V, VDS = 20 V; ID = 50 A
32
nC
4.7
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 10 V, VDS = 20 V,
ID = 50 A, RG = 2.5 W
tf
50
ns
23
18
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.83
TJ = 125°C
0.71
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 50 A
1.2
V
43
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 50 A
QRR
22
ns
22
40
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMYS2D4N04C
TYPICAL CHARACTERISTICS
120
10 V to 7 V
100
80
VGS = 4.8 V
60
40
0.4
0.8
1.6
1.2
2.0
80
TJ = 25°C
60
40
TJ = 125°C
TJ = −55°C
0
2.0
2.8
2.6
Figure 2. Transfer Characteristics
TJ = 25°C
IDS = 50 A
3.5
3.0
2.5
2.0
1.5
1.0
0.5
4
5
6
7
8
9
10
VGS, GATE VOLTAGE (V)
6.0
5.0
Figure 1. On−Region Characteristics
4.0
2.50
TJ = 25°C
VGS = 10 V
2.25
2.00
1.75
1.50
1.25
1.00
0
10
20
30
40
50
60
80
70
90 100
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.0
1.E−04
VGS = 10 V
ID = 50 A
1.6
IDSS, LEAKAGE (A)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
4.0
VGS, GATE−TO−SOURCE VOLTAGE (V)
4.5
1.8
3.0
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
0
5.0
0.0
100
20
20
0
VDS = 10 V
120
5.2 V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
140
5.6 V
6V
140
1.4
1.2
1.0
TJ = 150°C
1.E−05
TJ = 125°C
1.E−06
TJ = 85°C
1.E−07
0.8
0.6
−50 −25
0
25
50
75
100
125
150
175
1.E−08
0
5
10
15
20
25
30
35
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
40
NVMYS2D4N04C
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
1E+4
C, CAPACITANCE (pF)
CISS
1E+3
COSS
1E+2
1E+1
CRSS
VGS = 0 V
TJ = 25°C
f = 1 MHz
0
5
10
15
20
25
30
35
40
12
QT
10
8
6
QGD
QGS
4
VDS = 20 V
ID = 50 A
TJ = 25°C
2
0
0
10
30
20
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
1000
t, TIME (ns)
100
IS, SOURCE CURRENT (A)
VGS = 10 V
VDS = 20 V
ID = 50 A
tr
tf
td(off)
td(on)
10
1
1
10
10
TJ = −55°C
TJ = 125°C
TJ = 25°C
1
0.4
100
0.5
0.6
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
1000
TC = 25°C
VGS ≤ 10 V
0.01 ms
IDS (A)
IPEAK (A)
0.1 ms
100
1 ms
dc
10
1
TJ = 150°C
TJ(initial) = 25°C
10
TJ(initial) = 100°C
10 ms
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
10
1
100
1E−04
1E−03
VDS (V)
TIME IN AVALANCHE (s)
Figure 11. Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
1E−02
NVMYS2D4N04C
TYPICAL CHARACTERISTICS
100
RqJA (°C/W)
50% Duty Cycle
10
20%
10%
1
5%
2%
1%
0.1
0.01
Single Pulse
0.001
0.0000001 0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
NVMYS2D4N04CTWG
Marking
Package
Shipping†
2D4N04C
LFPAK4
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
5
NVMYS2D4N04C
PACKAGE DIMENSIONS
LFPAK4 5x6
CASE 760AB
ISSUE B
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
NVMYS2D4N04C/D