DATA SHEET
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MOSFET - Power, Single
N-Channel
V(BR)DSS
RDS(on) MAX
ID MAX
10.6 mW @ 10 V
100 V
57.8 A
15.9 mW @ 4.5 V
100 V, 10.6 mW, 57.8 A
N−Channel
NVTFS010N10MCL
D (5 − 8)
Features
Small Footprint (3.3 x 3.3 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
NVTFWS010N10MCLTAG − Wettable Flanks Product
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
G (4)
S (1, 2, 3)
8 7 6 5
DDD D
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current RqJC
(Notes 1, 2, 3)
TC = 25C
Power Dissipation
RqJC (Notes 1, 2)
Continuous Drain
Current RqJA
(Notes 1, 2, 3)
Steady
State
Value
Unit
VDSS
100
V
1 2 3 4
VGS
20
V
Top
ID
57.8
A
TC = 100C
TC = 25C
40.8
PD
TC = 100C
TA = 25C
Power Dissipation
RqJA (Notes 1, 2)
Symbol
Steady
State
ID
A
11.7
8.3
3.2
IDM
232
A
IS
64.8
A
TJ, Tstg
−55 to
+175
C
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 2.9 A)
EAS
526
mJ
Lead Temperature for Soldering Purposes
(1/8 from case for 10 s)
TL
TA = 100C
TC = 25C, tp = 10 ms
Source Current
Operating Junction and Storage Temperature
Range
W
1.6
260
C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
WDFN8
(3.3x3.3, 0.65 P)
CASE 511DY
38.9
PD
Pulsed Drain Current
GS S S
Pin 1
Bottom
W
77.8
TA = 100C
TA = 25C
Pin 1
Symbol
Value
Unit
Junction−to−Case − Steady State (Note 2)
RqJC
1.93
C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
46.6
WDFNW8
(Full−Cut m8FL Fused WF)
CASE 515AP
MARKING DIAGRAM
N10x
AYWW
N10x = Specific Device Code
x = L or W
A
= Assembly Location
Y
= Year Code
WW = Work Week Code
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Continuous DC current rating. Maximum current for pulses as long as 1
second is higher but is dependent on pulse duration and duty cycle.
Semiconductor Components Industries, LLC, 2018
September, 2022 − Rev. 1
1
Publication Order Number:
NVTFS010N10MCL/D
NVTFS010N10MCL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
100
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
64
VGS = 0 V,
VDS = 80 V
mV/C
TJ = 25C
1.0
TJ = 125C
250
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 85 mA
100
mA
nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
1.0
1.5
3.0
−5.3
VGS = 10 V
ID = 15 A
9.1
10.6
VGS = 4.5 V
ID = 12 A
13.5
15.9
gFS
VDS =5 V, ID = 15 A
V
mV/C
54
mW
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
1530
2150
Output Capacitance
COSS
625
875
Reverse Transfer Capacitance
CRSS
10
18
VGS = 0 V, f = 1 MHz, VDS = 50 V
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 50 V; ID = 15 A
10
Total Gate Charge
QG(TOT)
VGS = 10 V, VDS = 50 V; ID = 15 A
22
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
VGS = 10 V, VDS = 50 V; ID = 15 A
30
4.0
pF
nC
nC
3.0
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
9.0
VGS = 10 V, VDS = 50 V,
ID = 15 A, RG = 6 W
tf
3.0
ns
28
5.0
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Reverse Recovery Charge
QRR
Reverse Recovery Time
tRR
Reverse Recovery Charge
QRR
VGS = 0 V, IS = 15 A
IF = 8 A, di/dt = 300 A/ms
IF = 8 A, di/dt = 1000 A/ms
0.8
1.3
V
22
36
ns
35
56
nC
17
30
ns
79
126
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVTFS010N10MCL
TYPICAL CHARACTERISTICS (TJ = 25C UNLESS OTHERWISE NOTED)
80
VGS = 10 V
VDS = 5 V
VGS = 8 V
120
90
VGS = 6 V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
150
VGS = 4.5 V
60
VGS = 3.5 V
30
0
VGS = 3 V
0
1
2
3
4
60
40
20
0
5
TJ = 150 oC
TJ = −55oC
1
Figure 1. On Region Characteristics
4
60
40
20
VGS = 4.5 V
20
10
VGS = 10 V
2
3
0
4
5
6
7
8
9
10
VGS, GATE TO SOURCE VOLTAGE (V)
0
30
60
90
120
150
ID, DRAIN CURRENT (A)
Figure 3. On-Resistance
vs. Gate to Source Voltage
Figure 4. On−Resistance vs. Drain
Current and Gate Voltage
IDSS , REVERSE LEAKAGE CURRENT (mA)
2.2
2.0
6
30
TJ = 25 oC
0
5
40
ID = 15 A
R DS(on), ON−RESISTANCE (mW)
rDS(on), DRAIN TO
3
Figure 2. Transfer Characteristics
80
SOURCE ON−RESISTANCE (mW)
2
VGS, GATE TO SOURCE VOLTAGE (V)
VDS, DRAIN TO SOURCE VOLTAGE (V)
NORMALIZED
DRAIN TO SOURCE ON−RESISTANCE
TJ = 25 oC
ID = 15 A
VGS = 10 V
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0
25 50 75 100 125 150 175
−75 −50 −25
TJ, JUNCTION TEMPERATUREo(C)
1.0E−01
1.0E−02
1.0E−03
1.0E−04
TJ = 175 oC
TJ = 150 oC
TJ = 125 oC
TJ = 85 oC
1.0E−05
1.0E−06
TJ = 25 oC
1.0E−07
1.0E−08
10
20
30
40
50
60
70
80
VDS , DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. Normalized On Resistance
vs. Junction Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NVTFS010N10MCL
TYPICAL CHARACTERISTICS (TJ = 25C UNLESS OTHERWISE NOTED)
10000
10
1000
Coss
100
Crss
10
f = 1 MHz
VGS = 0 V
1
0.1
1
QTOT
VGS, GATE TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
Ciss
10
8
6
QGS
4
QGD
2
0
100
VDS = 50 V
ID = 15 A
0
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 10 V
IS, REVERSE DRAIN CURRENT (A)
t SW , SWITCHING TIME (nS)
100
Tf
VDS = 50 V
Tr
10
1
Td(on)
0
5
10
15
20
25
30
35
40
20
25
Figure 8. Gate Charge
Characteristics
Td(off)
ID = 15 A
15
Qg, GATE CHARGE (nC)
Figure 7. Capacitance vs. Drain
to Source Voltage
200
10
45
150
100
VGS = 0 V
10
1
TJ = 150 oC
TJ = 25 oC
0.1
0.01
TJ = −55oC
0.001
0.0
50
0.2
0.4
0.6
0.8
1.0
RG , GATE RESISTANCE ( W )
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
Figure 10. Source to Drain Diode
Forward Voltage vs. Source Current
300
1.2
100
10 m s
10
10
THIS AREA IS
LIMITED BY r DS(on)
100 m s
1
1
0.1
1 ms
10 ms
100 ms/DC
CURVE BENT TO
MEASURED DATA
0.1
1
10
100
TJ (initial) = 25 oC
Ipeak (A)
ID, DRAIN CURRENT (A)
100
0.1
0.00001
300
TJ (initial) = 100 oC
0.0001
0.001
tAV, TIME IN AVALANCHE (s)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe Operating Area
Figure 12. Unclamped Inductive
Switching Capability
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4
0.01
NVTFS010N10MCL
TYPICAL CHARACTERISTICS (CONTINUED)
100
R(t) (C/W)
10
1
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
SINGLE PULSE
0.01
−6
10
10
−5
10
−4
10
−3
10
−2
10
−1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Junction−to−Case Transient Thermal Response Curve
DEVICE ORDERING INFORMATION
Marking
Package
Shipping†
NVTFS010N10MCLTAG
N10L
WDFN8
(Pb−Free)
1500 / Tape & Reel
NVTFWS010N10MCLTAG
N10W
WDFNW8
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P
CASE 511DY
ISSUE A
DATE 21 AUG 2018
GENERIC
MARKING DIAGRAM*
XXXX
AYWW
XXXX
A
Y
WW
= Specific Device Code
= Assembly Location
= Year Code
= Work Week Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON90827G
WDFN8 3.3x3.3, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFNW8 3.3x3.3, 0.65P (Full−Cut m8FL Fused WF)
CASE 515AP
ISSUE O
GENERIC
MARKING DIAGRAM*
XXXX
AYWWG
G
DOCUMENT NUMBER:
DESCRIPTION:
DATE 25 AUG 2020
XXXX = Specific Device Code
*This information is generic. Please refer to
A
= Assembly Location
device data sheet for actual part marking.
Y
= Year
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
WW = Work Week
not follow the Generic Marking.
G
= Pb−Free Package
(Note: Microdot may be in either location)
98AON24557H
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
WDFNW8 3.3x3.3, 0.65P (Full−Cut m8FL Fused WF)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
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