DATA SHEET
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MOSFET – Power, Single
N-Channel, m8FL
V(BR)DSS
30 V, 5.9 mW, 55 A
RDS(on) MAX
5.9 mW @ 10 V
30 V
NVTFS4C08N
•
N−Channel MOSFET
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
NVTFS4C08NWF − Wettable Flanks Product
NVT Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
D (5−8)
G (4)
S (1,2,3)
MARKING
DIAGRAM
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
17
A
TA = 25°C
Continuous Drain
Current RqJA
(Notes 1, 2, 4)
Power Dissipation RqJA
(Note 1, 2, 4)
Continuous Drain
Current RqJC (Note 1,
3, 4)
TA = 100°C
TA = 25°C
Steady
State
TA = 25°C
TA = 25°C
55
PD
TA = 100°C
TA = 25°C, tp = 10 ms
Operating Junction and Storage Temperature
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche Energy
(TJ = 25°C, IL = 20 Apk, L = 0.1 mH)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
W
1.6
ID
WDFN8
CASE 511AB
1
WDFNW8
CASE 515AN
4C08
3.1
PD
TA = 100°C
TA = 100°C
Power Dissipation
RqJC (Note 1, 3, 4)
Pulsed Drain Current
12
39
A
31
W
15
IDM
253
A
TJ,
Tstg
−55 to
+175
°C
IS
28
A
EAS
20
mJ
TL
260
°C
55 A
9.0 mW @ 4.5 V
Features
•
•
•
•
•
ID MAX
08WF
A
Y
WW
G
1
S
S
S
G
XXXX
AYWWG
G
D
D
D
D
= Specific Device Code for
NVMTS4C08N
= Specific Device Code of
NVTFS4C08NWF
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Junction−to−Case − Steady State (Drain)
(Notes 1 and 4)
RqJC
4.9
Junction−to−Ambient – Steady State
(Notes 1 and 2)
RqJA
48
Unit
°C/W
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2 2 oz. Cu pad.
3. Assumes heat−sink sufficiently large to maintain constant case temperature
independent of device power.
4. Continuous DC current rating. Maximum current for pulses as long as
1 second is higher but is dependent on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2014
March, 2022 − Rev. 3
1
Publication Order Number:
NVTFS4C08N/D
NVTFS4C08N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
13.8
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.2
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
VGS(TH)/TJ
RDS(on)
1.3
5.0
mV/°C
VGS = 10 V
ID = 30 A
4.7
5.9
VGS = 4.5 V
ID = 18 A
7.2
9.0
mW
Forward Transconductance
gFS
VDS = 1.5 V, ID = 15 A
42
S
Gate Resistance
RG
TA = 25°C
1.0
W
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
1113
VGS = 0 V, f = 1 MHz, VDS = 15 V
702
VGS = 0 V, VDS = 15 V, f = 1 MHz
0.035
CRSS
pF
39
Capacitance Ratio
CRSS/CISS
Total Gate Charge
QG(TOT)
8.4
Threshold Gate Charge
QG(TH)
1.8
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
3.3
Gate Plateau Voltage
VGP
3.4
V
18.2
nC
Total Gate Charge
VGS = 4.5 V, VDS = 15 V; ID = 30 A
QG(TOT)
VGS = 10 V, VDS = 15 V; ID = 30 A
nC
3.5
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
9.0
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
33
tf
4.0
td(ON)
7.0
tr
td(OFF)
VGS = 10 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
ns
15
26
ns
19
3.0
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
VSD
VGS = 0 V,
IS = 10 A
TJ = 25°C
0.79
TJ = 125°C
0.66
tRR
ta
tb
1.1
V
28.3
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
QRR
14.5
ns
13.8
15.3
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
NVTFS4C08N
TYPICAL CHARACTERISTICS
5.5 V −
10 V
ID, DRAIN CURRENT (A)
80
3.8 V
70
60
3.6 V
50
3.4 V
40
3.2 V
30
3.0 V
20
0
2.8 V
60
50
40
30
0.5
1
1.5
2
2.5
TJ = 25°C
10
0
3
0
1.5
2
2.5
3
3.5
4
4.5
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 30 A
0.016
0.014
0.012
0.010
0.008
0.006
0.004
4.0
5.0
6.0
7.0
8.0
9.0
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
5
0.010
TJ = 25°C
0.009
0.008
VGS = 4.5 V
0.007
0.006
VGS = 10 V
0.005
0.004
0.003
0.002
10
20
30
40
50
60
70
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. VGS
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10000
1.80
VGS = 0 V
ID = 30 A
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
1
VGS, GATE−TO−SOURCE VOLTAGE (V)
0.018
1.60
0.5
TJ = −55°C
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.020
0.002
3.0
TJ = 125°C
20
TJ = 25°C
0
VDS = 3 V
70
4V
10
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
80
4.2 V
4.5 V
ID, DRAIN CURRENT (A)
90
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
100
1.40
1.20
1.00
TJ = 150°C
TJ = 125°C
1000
TJ = 85°C
100
0.80
0.60
−50
−25
0
25
50
75
100
125
150
175
10
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
30
NVTFS4C08N
1800
VGS = 0 V
TJ = 25°C
C, CAPACITANCE (pF)
1600
1400
Ciss
1200
1000
Coss
800
600
400
200
0
Crss
0
5
10
15
20
25
30
VGS, GATE−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
6
4
Qgd
0
TJ = 25°C
VDD = 15 V
VGS = 10 V
ID = 30 A
Qgs
2
0
2
4
6
8
10
12
14
16
18
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
20
20
VDD = 15 V
ID = 15 A
VGS = 10 V
IS, SOURCE CURRENT (A)
tr
100
td(off)
10
VGS = 0 V
18
td(on)
tf
16
14
12
10
8
6
TJ = 125°C
4
TJ = 25°C
2
1
10
100
0
0.4
0.5
0.6
0.7
0.8
0.9
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
ID, DRAIN CURRENT (A)
t, TIME (ns)
QT
8
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1000
1
10
10 ms
10
100 ms
1
1 ms
VGS = 10 V
TC = 25°C
2
0.1 650 mm 2 oz Cu Pad
RDS(on) Limit
Thermal Limit
Package Limit
0.01
0.1
1
10 ms
dc
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
100
1.0
NVTFS4C08N
TYPICAL CHARACTERISTICS
100
Duty Cycle = 50%
RqJA(t) (°C/W)
10
20%
10%
5%
2%
1
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 12. Thermal Response
100
80
IPEAK, DRAIN CURRENT (A)
70
60
GFS (S)
50
40
30
20
10
0
0
5
TJ(initial) = 25°C
10
1
1.0E−06
10 15 20 25 30 35 40 45 50 55 60 65 70
TJ(initial) = 125°C
1.0E−05
1.0E−04
ID (A)
TAV, TIME IN AVALANCHE (s)
Figure 13. GFS vs. ID
Figure 14. Avalanche Characteristics
1.E−03
ORDERING INFORMATION
Package
Shipping†
NVTFS4C08NTAG
WDFN8
(Pb−Free)
1500 / Tape & Reel
NVTFS4C08NWFTAG
WDFNW8
(Pb−Free)
1500 / Tape & Reel
NVTFS4C08NTWG
WDFN8
(Pb−Free)
5000 / Tape & Reel
NVTFS4C08NWFTWG
WDFNW8
(Pb−Free)
5000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P
CASE 511AB
ISSUE D
1
SCALE 2:1
DATE 23 APR 2012
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
0.20 C
D
A
D1
B
2X
0.20 C
8 7 6 5
4X
E1 E
q
c
1 2 3 4
A1
TOP VIEW
0.10 C
A
e
SIDE VIEW
0.10
8X b
C A B
0.05
C
4X
DETAIL A
8X
e/2
1
0.42
4
INCHES
NOM
0.030
−−−
0.012
0.008
0.130 BSC
0.116
0.120
0.078
0.083
0.130 BSC
0.116
0.120
0.058
0.063
0.009
0.012
0.026 BSC
0.012
0.016
0.026
0.032
0.012
0.017
0.002
0.005
0.055
0.059
0_
−−−
MIN
0.028
0.000
0.009
0.006
MAX
0.031
0.002
0.016
0.010
0.124
0.088
0.124
0.068
0.016
0.020
0.037
0.022
0.008
0.063
12 _
0.65
PITCH
PACKAGE
OUTLINE
4X
0.66
M
E3
8
5
D2
BOTTOM VIEW
1
3.60
L1
GENERIC
MARKING DIAGRAM*
XXXXX
A
Y
WW
G
MILLIMETERS
MIN
NOM
MAX
0.70
0.75
0.80
0.00
−−−
0.05
0.23
0.30
0.40
0.15
0.20
0.25
3.30 BSC
2.95
3.05
3.15
1.98
2.11
2.24
3.30 BSC
2.95
3.05
3.15
1.47
1.60
1.73
0.23
0.30
0.40
0.65 BSC
0.30
0.41
0.51
0.65
0.80
0.95
0.30
0.43
0.56
0.06
0.13
0.20
1.40
1.50
1.60
0_
−−−
12 _
SOLDERING FOOTPRINT*
L
G
SEATING
PLANE
DETAIL A
K
E2
C
6X
0.10 C
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
E3
e
G
K
L
L1
M
q
XXXXX
AYWWG
G
0.75
2.30
0.57
0.47
2.37
3.46
DIMENSION: MILLIMETERS
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30561E
WDFN8 3.3X3.3, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFNW8 3.3x3.3, 0.65P (Full−Cut m8FL WF)
CASE 515AN
ISSUE O
GENERIC
MARKING DIAGRAM*
XXXX
AYWWG
G
DOCUMENT NUMBER:
DESCRIPTION:
DATE 25 AUG 2020
XXXX = Specific Device Code
*This information is generic. Please refer to
A
= Assembly Location
device data sheet for actual part marking.
Y
= Year
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
WW = Work Week
not follow the Generic Marking.
G
= Pb−Free Package
(Note: Microdot may be in either location)
98AON24556H
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
WDFNW8 3.3x3.3, 0.65P (Full−Cut m8FL WF)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
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