NVTFS6H888NLTAG

MOSFET - Power, Single N-Channel 80 V, 50 mW, 14 A NVTFS6H888NL Features • • • • • • www.onsemi.com Small Footprint (3.3 x 3.3 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses NVTFS6H888NLWF − Wettable Flanks Product AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant V(BR)DSS RDS(ON) MAX ID MAX 50 mW @ 10 V 80 V 14 A 67 mW @ 4.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RqJC (Notes 1, 2, 3, 4) TC = 25°C Power Dissipation RqJC (Notes 1, 2, 3) Continuous Drain Current RqJA (Notes 1, 3, 4) Steady State Value Unit VDSS 80 V VGS ±20 V ID 14 A TC = 100°C TC = 25°C PD Steady State Pulsed Drain Current S (1, 2, 3) 12 ID A 4.9 PD W 2.9 1.5 IDM 49 A TJ, Tstg −55 to +175 °C IS 20 A Single Pulse Drain−to−Source Avalanche Energy (IL(pk) = 0.6 A) EAS 92 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Operating Junction and Storage Temperature Range Source Current (Body Diode) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS (Note 1) Parameter Symbol Value Unit Junction−to−Case − Steady State (Note 3) RqJC 6.4 °C/W Junction−to−Ambient − Steady State (Note 3) RqJA 52 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Psi (Y) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface. 3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 4. Continuous DC current rating. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2019 November, 2020 − Rev. 1 MARKING DIAGRAMS 3.5 TA = 100°C TA = 25°C, tp = 10 ms D (5 − 8) W 23 TA = 100°C TA = 25°C N−Channel G (4) 10 TC = 100°C TA = 25°C Power Dissipation RqJA (Notes 1, 3) Symbol 1 1 WDFN8 (m8FL) CASE 511AB WDFNW8 (Full−Cut m8FL) CASE 515AN 1 S S S G XXXX AYWWG G D D D D XXXX AYWWG G XXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: NVTFS6H888NL/D NVTFS6H888NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min V(BR)DSS VGS = 0 V, ID = 250 mA 80 Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current VGS = 0 V, VDS = 80 V V TJ = 25°C 10 TJ = 125°C 100 IGSS VDS = 0 V, VGS = 20 V VGS(TH) VGS = VDS, ID = 15 mA 100 mA nA ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Threshold Temperature Coefficient Drain−to−Source On Resistance VGS(TH)/TJ RDS(on) Forward Transconductance gFS 1.2 2.0 −5 V mV/°C VGS = 10 V ID = 5 A 41 50 mW VGS = 4.5 V ID = 5 A 53 67 mW VDS = 8 V, ID = 10 A 20 S CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 258 VGS = 0 V, f = 1 MHz, VDS = 40 V 36 Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) 0.7 Gate−to−Source Charge QGS 1.2 Gate−to−Drain Charge QGD Plateau Voltage Total Gate Charge pF 3 VGS = 10 V, VDS = 40 V; ID = 10 A VGS = 4.5 V, VDS = 40 V; ID = 10 A 6 nC 1.0 VGP 3.3 V QG(TOT) 3 nC SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr td(OFF) 6 VGS = 4.5 V, VDS = 64 V, ID = 10 A, RG = 2.5 W tf 15 ns 9 3 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 5 A TJ = 25°C 0.85 TJ = 125°C 0.73 tRR ta tb 1.2 V 23 VGS = 0 V, dIS/dt = 100 A/ms, IS = 10 A QRR 15 ns 7 13 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NVTFS6H888NL TYPICAL CHARACTERISTICS 14 12 3.4 V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 12 3.6 V 10 3.2 V 8 6 3.0 V 4 2.8 V 10 8 6 2 0 0 0 1 2 4 3 5 0 1.5 2.0 TJ = −55°C 2.5 3.0 50 45 40 6 5 4 7 9 8 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 4.0 3.5 Figure 2. Transfer Characteristics 55 57 TJ = 25°C 55 VGS = 4.5 V 53 51 49 47 45 43 VGS = 10 V 41 39 37 35 1 2 3 5 4 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1000 2.5 VGS = 10 V ID = 5 A 100 2.0 IDSS, LEAKAGE (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE 1.0 Figure 1. On−Region Characteristics TJ = 25°C ID = 5 A 1.5 1.0 0.5 −50 0.5 VGS, GATE−TO−SOURCE VOLTAGE (V) 60 3 TJ = 125°C VDS, DRAIN−TO−SOURCE VOLTAGE (V) 65 35 TJ = 25°C 4 2 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) 14 VGS = 10 V to 3.8 V −25 0 25 50 75 100 125 150 175 10 TJ = 175°C TJ = 150°C 1 T = 125°C J 0.1 TJ = 85°C 0.01 TJ = 25°C 0.001 5 15 25 35 45 55 65 75 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 NVTFS6H888NL 1000 C, CAPACITANCE (pF) CISS 100 COSS 10 0 t, TIME (ns) 100 10 CRSS 20 30 40 50 60 70 80 6 5 QGS 4 QGD 3 VDS = 40 V ID = 10 A TJ = 25°C 2 1 0 1 0 2 3 5 4 Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge VGS = 4.5 V VDS = 64 V ID = 10 A 6 VGS = 0 V td(off) tr tf 1 TJ = 125°C 0.1 1 10 0.3 100 0.4 TJ = −55°C TJ = 25°C 0.5 0.6 0.7 0.8 0.9 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current TA = 25°C Single Pulse VGS ≤ 10 V 10 TJ(initial) = 25°C IPEAK (A) ID, DRAIN CURRENT (A) 100 8 7 Figure 7. Capacitance Variation td(on) 1000 9 QG, TOTAL GATE CHARGE (nC) 10 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) IS, SOURCE CURRENT (A) 1 VGS = 0 V TJ = 25°C f = 1 MHz VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS 10 1 TJ(initial) = 100°C 1 0.1 RDS(on) Limit Thermal Limit Package Limit 0.1 1 10 10 ms 10 ms 0.5 ms 1 ms 100 1000 0.1 0.00001 0.0001 0.001 0.01 VDS, DRAIN−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s) Figure 11. Safe Operating Area Figure 12. Maximum Drain Current vs. Time in Avalanche www.onsemi.com 4 NVTFS6H888NL TYPICAL CHARACTERISTICS 100 R(t) (°C/W) 50% Duty Cycle 20% 10 10% 5% 1 2% 1% 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 1 0.1 10 100 1000 PULSE TIME (sec) Figure 13. Thermal Response DEVICE ORDERING INFORMATION Marking Package Shipping† NVTFS6H888NLTAG 888L WDFN8 (Pb−Free) 1500 / Tape & Reel NVTFS6H888NLWFTAG 88LW WDFN8 (Pb−Free, Wettable Flanks) 1500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFN8 3.3x3.3, 0.65P CASE 511AB ISSUE D 1 SCALE 2:1 DATE 23 APR 2012 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 0.20 C D A D1 B 2X 0.20 C 8 7 6 5 4X E1 E q c 1 2 3 4 A1 TOP VIEW 0.10 C A e SIDE VIEW 0.10 8X b C A B 0.05 C 4X DETAIL A 8X e/2 1 0.42 4 INCHES NOM 0.030 −−− 0.012 0.008 0.130 BSC 0.116 0.120 0.078 0.083 0.130 BSC 0.116 0.120 0.058 0.063 0.009 0.012 0.026 BSC 0.012 0.016 0.026 0.032 0.012 0.017 0.002 0.005 0.055 0.059 0_ −−− MIN 0.028 0.000 0.009 0.006 MAX 0.031 0.002 0.016 0.010 0.124 0.088 0.124 0.068 0.016 0.020 0.037 0.022 0.008 0.063 12 _ 0.65 PITCH PACKAGE OUTLINE 4X 0.66 M E3 8 5 D2 BOTTOM VIEW 1 3.60 L1 GENERIC MARKING DIAGRAM* XXXXX A Y WW G MILLIMETERS MIN NOM MAX 0.70 0.75 0.80 0.00 −−− 0.05 0.23 0.30 0.40 0.15 0.20 0.25 3.30 BSC 2.95 3.05 3.15 1.98 2.11 2.24 3.30 BSC 2.95 3.05 3.15 1.47 1.60 1.73 0.23 0.30 0.40 0.65 BSC 0.30 0.41 0.51 0.65 0.80 0.95 0.30 0.43 0.56 0.06 0.13 0.20 1.40 1.50 1.60 0_ −−− 12 _ SOLDERING FOOTPRINT* L G SEATING PLANE DETAIL A K E2 C 6X 0.10 C DIM A A1 b c D D1 D2 E E1 E2 E3 e G K L L1 M q XXXXX AYWWG G 0.75 2.30 0.57 0.47 2.37 3.46 DIMENSION: MILLIMETERS = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98AON30561E WDFN8 3.3X3.3, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFNW8 3.3x3.3, 0.65P (Full−Cut m8FL WF) CASE 515AN ISSUE O GENERIC MARKING DIAGRAM* XXXX AYWWG G DOCUMENT NUMBER: DESCRIPTION: DATE 25 AUG 2020 XXXX = Specific Device Code *This information is generic. Please refer to A = Assembly Location device data sheet for actual part marking. Y = Year Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may WW = Work Week not follow the Generic Marking. G = Pb−Free Package (Note: Microdot may be in either location) 98AON24556H Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. WDFNW8 3.3x3.3, 0.65P (Full−Cut m8FL WF) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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