H-Bridge in APM16 Series
for LLC and Phase-shifted
DC-DC Converter
NXV65HR82DS1,
NXV65HR82DS2,
NXV65HR82DZ1,
NXV65HR82DZ2
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Features
• SIP or DIP H−Bridge Power Module for On−board Charger (OBC) in
•
•
•
•
•
•
EV or PHEV
5 kV/1 s Electrically Isolated Substrate for Easy Assembly
Creepage and Clearance per IEC60664−1, IEC 60950−1
Compact Design for Low Total Module Resistance
Module Serialization for Full Traceability
Lead Free, RoHS and UL94V−0 Compliant
Automotive Qualified per AEC Q101 and AQG324 Guidelines
APMCA−A16
16 LEAD
CASE MODGF
Applications
• DC−DC Converter for On−board Charger in EV or PHEV
Benefits
• Enable Design of Small, Efficient and Reliable System for Reduced
Vehicle Fuel Consumption and CO2 Emission
APMCA−B16
16 LEAD
CASE MODGJ
• Simplified Assembly, Optimized Layout, High Level of Integration,
and Improved Thermal Performance
MARKING DIAGRAM
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ZZZ ATYWW
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XXXX
ZZZ
AT
Y
W
NNN
= Specific Device Code
= Lot ID
= Assembly & Test Location
= Year
= Work Week
= Serial Number
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2020
April, 2021 − Rev. 2
1
Publication Order Number:
NXV65HR82D/D
NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2
Pin Configuration and Block Diagram
Figure 1. Pin Configuration
Table 1. PIN DESCRIPTION
Pin Number
Pin Name
Pin Description
1, 2
AC1
3
Q1 Sense
Phase 1 Leg of the H−Bridge
Source Sense of Q1
Gate Terminal of Q1
4
Q1 Gate
5, 6
B+
Positive Battery Terminal
7, 8
B−
Negative Battery Terminal
9
Q2 Sense
Source Sense of Q2
10
Q2 Gate
Gate Terminal of Q2
11
Q4 Sense
Source Sense of Q4
12
Q4 Gate
Gate Terminal of Q4
13
Q3 Sense
Source Sense of Q3
14
Q3 Gate
Gate Terminal of Q3
15, 16
AC2
Phase 2 Leg of the H−Bridge
Block Diagram
NXV65HR82DZ1/2 (No Capacitor)
NXV65HR82DS1/2 (With Capacitor)
Figure 2. Schematic
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NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2
Table 2. ABSOLUTE MAXIMUM RATINGS (TJ = 25°C, Unless Otherwise Specified)
Parameter
Symbol
Max
Unit
VDS (Q1~Q4)
Drain−to−Source Voltage
650
V
VGS (Q1~Q4)
Gate−to−Source Voltage
±20
V
Drain Current Continuous (TC = 25°C, VGS = 10 V) (Note 1)
26
A
ID (Q1~Q4)
Drain Current Continuous (TC = 100°C, VGS = 10 V) (Note 1)
17
A
PD
Power Dissipation (Note 1)
126
W
TJ
Maximum Junction Temperature
−55 to +150
°C
TC
Maximum Case Temperature
−40 to +125
°C
Storage Temperature
−40 to +125
°C
TSTG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum continuous current and power, without switching losses, to reach TJ = 150°C respectively at TC = 25°C and TC = 100°C; defined
by design based on MOSFET RDS(ON) and RqJC and not subject to production test
Table 3. SINGLE PULSE AVALANCHE ENERGY
Symbol
Parameter
Max
Unit
EAS (Q1~Q4)
Single Pulsed Avalanche Energy (Note 2)
510
mJ
EAS (Q1~Q4)
Single Pulsed Avalanche Energy (Note 2)
21
mJ
Avalanche Current
4.8
A
IAS
2. 510 mJ is characterized at TJ = 25°C, L = 44.3 mH, IAS = 4.8 A, VDD = 145 V.
21 mJ is 100% tested at TJ = 25°C, L = 1 mH, IAS = 4.8 A, VDD = 145 V.
Table 4. COMPONENTS (Note 3)
Device
Capacitor (Snubber)
AEC Q200 qualified
Parameter
Capacitance
Condition
Min
Typ
Max
Unit
TJ = 25°C
135
150
165
nF
−
630
−
V
Rated Voltage
3. These values are obtained from the specification provided by the manufacturer.
DBC Substrate
Compliance to RoHS Directives
0.63 mm Al2O3 alumina with 0.3 mm copper on both sides.
DBC substrate is NOT nickel plated.
The power module is 100% lead free and RoHS compliant
2000/53/C directive.
Lead Frame
Solder
OFC copper alloy, 0.50 mm thick. Plated with 8 um to
25.4 um thick Matte Tin
Solder used is a lead free SnAgCu alloy.
Solder presents high risk to melt at temperature beyond
210°C. Base of the leads, at the interface with the package
body, should not be exposed to more than 200°C during
mounting on the PCB or during welding to prevent the
re−melting of the solder joints.
Flammability Information
All materials present in the power module meet UL
flammability rating class 94V−0.
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NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2
Table 5. ELECTRICAL SPECIFICATIONS (TJ = 25°C, Unless Otherwise Specified)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
BVDSS
Drain−to−Source Breakdown Voltage
ID = 1 mA, VGS = 0 V
650
−
−
V
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 0.97 mA
3.0
−
5.0
V
RDS(ON)
Q1 – Q4 MOSFET On Resistance
VGS = 10 V, ID = 20 A
−
73
82
mW
RDS(ON)
Q1 – Q4 MOSFET On Resistance
VGS = 10 V, ID = 20 A, TJ = 125°C (Note 4)
−
133
−
mW
gFS
Forward Transconductance
VDS = 20 V, ID = 20 A (Note 4)
−
29
−
S
IGSS
Gate−to−Source Leakage Current
VGS = ±30 V, VDS = 0 V
−100
−
+100
nA
IDSS
Drain−to−Source Leakage Current
VDS = 650 V, VGS = 0 V
−
−
10
mA
VDS = 400 V
VGS = 0 V
f = 1 MHz
−
3608
−
pF
−
72.3
−
pF
−
5.56
−
pF
448
−
pF
DYNAMIC CHARACTERISTICS (Note 4)
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Coss(eff)
Effective Output Capacitance
VDS = 0 to 520 V
VGS = 0 V
−
Gate Resistance
f = 1 MHz
−
1.7
−
W
Total Gate Charge
VDS = 380 V
ID = 20 A
VGS = 0 to 10 V
−
79.7
−
nC
−
24.9
−
nC
−
31.9
−
nC
VDS = 400 V
ID = 20 A
VGS = 10 V
RG = 4.7 W
−
96
−
ns
−
54
−
ns
−
42
−
ns
Turn−off Time
−
117
−
ns
Turn−off Delay Time
−
84
−
ns
Turn−off Fall Time
−
33
−
ns
Rg
Qg(tot)
Qgs
Gate−to−Source Gate Charge
Qgd
Gate−to−Drain “Miller” Charge
SWITCHING CHARACTERISTICS (Note 4)
ton
Turn−on Time
td(on)
Turn−on Delay Time
tr
Turn−on Rise Time
toff
td(off)
tf
BODY DIODE CHARACTERISTICS
Source−to−Drain Diode Voltage
ISD = 20 A, VGS = 0 V
−
1.1
−
V
Trr
Reverse Recovery Time
−
107
−
ns
Qrr
Reverse Recovery Charge
VDS = 520 V, ID = 20 A,
dI/dt = 100 A/ms (Note 4)
−
430
−
nC
VSD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Defined by design, not subject to production test
Table 6. THERMAL RESISTANCE
Parameters
Min
Typ
Max
Unit
RθJC (per chip)
Q1~Q4 Thermal Resistance Junction−to−Case (Note 5)
−
0.7
0.99
°C/W
RθJS (per chip)
Q1~Q4 Thermal Resistance Junction−to−Sink (Note 6)
−
1.32
−
°C/W
5. Test method compliant with MIL STD 883−1012.1, from case temperature under the chip to case temperature measured below the package
at the chip center, Cosmetic oxidation and discoloration on the DBC surface allowed
6. Defined by thermal simulation assuming the module is mounted on a 5 mm Al−360 die casting material with 30 um of 1.8 W/mK thermal
interface material
Table 7. ISOLATION (Isolation resistance at tested voltage from the base plate to control pins or power terminals.)
Test
Leakage @ Isolation Voltage (Hi−Pot)
Test Conditions
VAC = 5 kV, 50 Hz
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4
Isolation Resistance
Unit
100M <
W
NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2
PARAMETER DEFINITIONS
Reference to Table 5: Parameter of Electrical Specifications
BVDSS
Q1 – Q4 MOSFET Drain−to−Source Breakdown Voltage
The maximum drain−to−source voltage the MOSFET can endure without the avalanche breakdown of the body− drain
P−N junction in off state.
The measurement conditions are to be found in Table 5.
The typ. Temperature behavior is described in Figure 13
VGS(th)
Q1 – Q4 MOSFET Gate to Source Threshold Voltage
The gate−to−source voltage measurement is triggered by a threshold ID current given in conditions at Table 11.
The typ. Temperature behavior can be found in Figure 12
RDS(ON)
Q1 – Q4 MOSFET On Resistance
RDS(on) is the total resistance between the source and the drain during the on state.
The measurement conditions are to be found in Table 5.}
The typ behavior can be found in Figure 10 and Figure 11 as well as Figure 17
gFS
Q1 – Q4 MOSFET Forward Transconductance
Transconductance is the gain in the MOSFET, expressed in the Equation below.
t describes the change in drain current by the change in the gate−source bias voltage: gfs = [ −DIDS / DVGS ]VDS
IGSS
Q1 – Q4 MOSFET Gate−to−Source Leakage Current
The current flowing from Gate to Source at the maximum allowed VGS
The measurement conditions are described in the Table 5.
IDSS
Q1 – Q4 MOSFET Drain−to−Source Leakage Current
Drain – Source current is measured in off state while providing the maximum allowed drain−to-source voltage and the
gate is shorted to the source.
IDSS has a positive temperature coefficient.
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NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2
Figure 3. Timing Measurement Variable Definition
Table 8. PARAMETER OF SWITCHING CHARACTERISTICS
Turn−On Delay (td(on)):
Rise Time (tr):
Turn−On Time (ton):
Turn−Off Delay (td(off)):
Fall Time (tf):
Turn−Off Time (toff):
This is the time needed to charge the input capacitance, Ciss, before the load current ID starts flowing.
The measurement conditions are described in the Table 5.
For signal definition please check Figure 3 above.
The rise time is the time to discharge output capacitance, Coss.
After that time the MOSFET conducts the given load current ID.
The measurement conditions are described in the Table 5.
For signal definition please check Figure 3 above.
Is the sum of turn−on−delay and rise time
td(off) is the time to discharge Ciss after the MOSFET is turned off.
During this time the load current ID is still flowing
The measurement conditions are described in the Table 5.
For signal definition please check Figure 3 above.
The fall time, tf, is the time to charge the output capacitance, Coss.
During this time the load current drops down and the voltage VDS rises accordingly.
The measurement conditions are described in the Table 5.
For signal definition please check Figure 3 above.
Is the sum of turn−off−delay and fall time
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NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2
1.2
30
1.0
25
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
TYPICAL CHARACTERISTICS
0.8
0.6
0.4
RqJC = 0.99°C/W
0.2
0
0
25
50
75
100
125
20
15
10
RqJC = 0.99°C/W
5
0
150
VGS = 10 V
25
50
TC, CASE TEMPERATURE (°C)
TJ = 25°C
20
TJ = 150°C
15
10
TJ = −55°C
0
2
80
3
4
6
7
VGS = 0 V
1
TJ = 150°C
0.1
TJ = −55°C
0.01
TJ = 25°C
0
0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Transfer Characteristics
Figure 7. Forward Diode
80
10 V
8V
50
30
6.5 V
20
6V
10
5.5 V
5V
5
10
15
10 V
70
7V
40
0
20
10
0.001
8
60
0
150
VGS, GATE TO SOURCE VOLTAGE (V)
VGS = 20 V
70
5
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
35
5
ID, DRAIN CURRENT (A)
IS, REVERSE DRAIN CURRENT (A)
VDS = 20 V
25
125
Figure 5. Maximum Continuous ID vs. Case
Temperature
45
30
100
TC, CASE TEMPERATURE (°C)
Figure 4. Normalized Power Dissipation vs. Case
Temperature
40
75
VGS = 20 V
60
8V
50
7V
40
6.5 V
30
6V
20
5.5 V
10
0
20
5V
0
5
10
15
VDS, DRAIN−SOURCE VOLTAGE (V)
VDS, DRAIN−SOURCE VOLTAGE (V)
Figure 8. Saturation (255C)
Figure 9. Saturation (1505C)
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20
NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2
TYPICAL CHARACTERISTICS (continued)
RDS(ON), NORMALIZED
DRAIN−SOURCE ON−RESISTANCE
300
200
TJ = 150°C
100
0
Vth, NORMALIZED GATE THRESHOLD VOLTAGE
2.5
ID = 20 A
TJ = 25°C
6
8
10
12
1.0
0.5
0
−75 −50 −25
14
0
25
50
75
100 125 150 175
VGS, GATE TO SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. On−Resistance vs. Gate−to−Source
Voltage
Figure 11. RDS(norm) vs. Junction Temperature
1.2
ID = 0.97 mA
1.1
1
0.9
0.8
0.7
0.6
−75 −50 −25
0
25
50
75
ID = 1 mA
1.1
1.0
0.9
0.8
−75 −50 −25
100 125 150 175
0
25
50
75
100 125 150 175
TJ, AMBIENT TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Normalized Vth vs. Temperature
Figure 13. Breakdown Voltage vs. Temperature
20
100000
10000
CAPACITANCE (pF)
16
Eoss (mJ)
1.5
1.2
12
8
4
0
ID = 20 A
VGS = 10 V
2.0
Bvdss, NORMALIZED DRAIN TO
SOURCE BREAKDOWN VOLTAGE
RDS(ON), ON−RESISTANCE (mW)
400
1000
100
200
300
400
500
600
10
0
0.1
700
Coss
100
1
0
Ciss
f = 1 MHz
VGS = 0 V
1
Crss
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 14. Eoss vs. Drain−to−Source Voltage
Figure 15. Capacitance Variation
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1000
NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2
TYPICAL CHARACTERISTICS (continued)
10
0.10
130 V
400 V
Vgs (V)
6
4
2
0
0
15
30
45
60
75
0.09
RDS(ON), DRAIN−SOURCE
ON−RESISTANCE (V)
380 V
8
0.08
VGS = 10 V
0.07
VGS = 20 V
0.06
0.05
90
0
20
40
60
CHARGE (nC)
ID, DRAIN CURRENT (A)
Figure 16. Gate Charge
Figure 17. RDS(ON) vs. ID
80
1000
For temperature above 25°C
Derate peak current as follows:
100 ms
10
RDS(ON) LIMIT
1 ms
1
0.1
SINGLE PULSE
RqJC = 0.99°C/W
TC = 25°C
1
RDS(on) Limit
Thermal Limit
Package Limit
10
100
10 ms
100 ms/
DC
1000
IDM, PEAK CURRENT (A)
100
I + I2
Ǹ
* b 2 * 4ac
2a
Notes:
RqJC = 0.99°C/W
Peak TJ = PDM x ZqJC(t)+ TC
Duty Cycle, D = t1 / t2
Limited IDM 203 A
100
Single Pulse
10
0.000001 0.00001
0.0001
0.001
0.01
0.1
VDS, DRAIN−SOURCE VOLTAGE (V)
t, PULSE WIDTH (s)
Figure 18. Safe Operating Area
Figure 19. Peak Current Capability
10
ZqJC, EFFECTIVE TRANSIENT
THERMAL RESISTANCE (°C/W)
ID, DRAIN CURRENT (A)
1000
1
Duty cycle = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
Notes:
ZqJC(t) = r(t) x RqJC
RqJC = 0.99°C/W
Peak TJ = PDM x ZqJC(t) + TC
Duty Cycle, D = t1 / t2
0.01
Single pulse
0.001
0.00001
0.0001
0.001
0.01
t, PULSE TIME (s)
Figure 20. Transient Thermal Impedance
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0.1
1
1
NXV65HR82DS1, NXV65HR82DS2, NXV65HR82DZ1, NXV65HR82DZ2
ORDERING INFORMATION
Part Number
Package
Lead Forming
Snubber
Capacitor Inside
DBC
Material
NXV65HR82DS1
APM16−CAA
Y−Shape
Yes
Al2O3
Yes
−40°C~125°C
Tube
NXV65HR82DS2
APM16−CAB
L−Shape
Yes
Al2O3
Yes
−40°C~125°C
Tube
NXV65HR82DZ1
APM16−CAA
Y−Shape
No
Al2O3
Yes
−40°C~125°C
Tube
NXV65HR82DZ2
APM16−CAB
L−Shape
No
Al2O3
Yes
−40°C~125°C
Tube
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Pb−Free and
Operating
RoHS Compliant Temperature (TA)
Packing
Method
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
APMCA−A16 / 16LD, AUTOMOTIVE MODULE
CASE MODGF
ISSUE C
GENERIC
MARKING DIAGRAM*
XXXXXXXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
DOCUMENT NUMBER:
DESCRIPTION:
XXXX
ZZZ
AT
Y
W
NNN
98AON94732G
= Specific Device Code
= Lot ID
= Assembly & Test Location
= Year
= Work Week
= Serial Number
DATE 03 NOV 2021
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
APMCA−A16 / 16LD, AUTOMOTIVE MODULE
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
APMCA−B16 / 16LD, AUTOMOTIVE MODULE
CASE MODGJ
ISSUE C
GENERIC
MARKING DIAGRAM*
XXXXXXXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
DOCUMENT NUMBER:
DESCRIPTION:
XXXX
ZZZ
AT
Y
W
NNN
98AON97133G
= Specific Device Code
= Lot ID
= Assembly & Test Location
= Year
= Work Week
= Serial Number
DATE 03 NOV 2021
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
APMCA−B16 / 16LD, AUTOMOTIVE MODULE
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
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