P2042AF-08TR

P2042A LCD Panel EMI Reduction IC Features Product Description • FCC approved method of EMI attenuation • Provides up to 15dB of EMI suppression • Generates a low EMI spread spectrum clock of the input frequency • Input frequency range: 30MHz -110MHz. • Output frequency range: 30MHz -110MHz • Optimized for 32.5MHz, 54MHz, 65MHz, 74MHz and 108MHz pixel clock frequencies • Internal loop filter minimizes external components and The P2042A is a versatile spread spectrum frequency modulator designed specifically for digital flat panel applications. The P2042A reduces electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of down stream clock and data dependent signals. The P2042A allows significant system cost savings by reducing the number of circuit board layers ferrite beads, shielding and other passive components that are traditionally required to pass EMI regulations. board space • Eight selectable high spread ranges up to ±2% • Selectable Center Spread options • SSON# control pin for spread spectrum enable and disable options • Low cycle-to-cycle jitter • 3.3V ± 0.3V operating range • CMOS design • Supports most mobile graphic accelerator and LCD timing controller specifications • Available in 8-pin TSSOP Package The P2042A uses the most efficient and optimized modulation profile approved by the FCC and is implemented in a proprietary all digital method. The P2042A modulates the output of a single PLL in order to “spread” the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal’s bandwidth is called ‘spread spectrum clock generation’. Applications The P2042A is targeted towards digital flat panel applications for notebook PCs, palm-size PCs, office automation equipments and LCD monitors. VDD Block Diagram SR0 CP1 CP0 SSON# PLL Modulation CLKIN Frequency Divider Feedback Divider Phase Detector Loop Filter VCO Output Divider ModOUT VSS ©2010 SCILLC. All rights reserved. November 2012 – Rev. 4 Publication Order Number: P2042/D P2042A Pin Configuration CLKIN 1 VDD 8 CP0 2 7 SR0 P2042A CP1 3 6 ModOUT VSS 4 5 SSON# Pin Description Pin# Pin Name Type Description 1 CLKIN I 2 CP0 I 3 CP1 I 4 VSS P Ground to entire chip. Connect to system ground. 5 SSON# I Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal pull-low resistor. 6 ModOUT O Spread spectrum clock output. 7 SR0 I Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor. Refer to Modulation Selection Table. 8 VDD P Power supply for the entire chip. External reference frequency input. Connect to externally generated reference signal. Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor. Refer to Modulation Selection Table. Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor. Refer to Modulation Selection Table. Modulation Selection Spreading Range (± %) CP0 CP1 SR0 32.5MHz 54MHz 65MHz 81MHz 108MHz 0 0 0 1.75 1.53 1.41 1.27 1.1 0 0 1 1.89 1.7 1.55 1.4 1.2 0 1 0 1.39 1.2 1.1 1.0 0.9 0 1 1 2.1 1.85 1.7 1.55 1.35 1 0 0 0.74 0.6 0.57 0.52 0.45 1 0 1 1.1 0.93 0.86 0.77 0.68 1 1 0 0.32 0.3 0.28 0.26 0.23 1 1 1 0.58 0.5 0.45 0.4 0.36 Modulation Rate (KHz) (FIN /40) * 62.89 KHz P2042A Spread Spectrum Selection The Modulation Selection Table defines the possible spread spectrum options. The optimal setting should minimize system EMI to the fullest without affecting system performance. The spreading is described as a percentage deviation of the center frequency. (Note: The center frequency is the frequency of the external reference input on CLKIN, pin1). For example, P2042A is designed for high-resolution, flat panel applications and is able to support an XGA (1024 x 768) flat panel operating at 65MHz (FIN) clock speed. A spreading selection of CP0=0, CP1=1 and SR0=0 provides a percentage deviation of ±1.00% from FIN. This results in the frequency on ModOUT being swept from 65.65 to 64.35MHz at a modulation rate of 102.19KHz. Refer to Modulation Selection Table. The example in the following illustration is a common EMI reduction method for a notebook LCD panel and has already been implemented by most of the leading OEM and mobile graphic accelerator manufacturers. Application Schematic for Mobile LCD Graphics Controllers +3.3V 65MHz from graphics accelerator 1 CLKIN VDD 8 2 CP0 SR0 7 3 CP1 ModOUT 6 4 VSS 0.1µF Modulated 65MHz signal with ±1.00% deviation and modulation rate of 102.19KHz. This signal is connected back to the spread spectrum input pin (SSIN) of the graphics accelerator. SSON# 5 P2042A Digital control for the SS enable or disable. P2042A Absolute Maximum Ratings Symbol VDD, VIN TSTG Rating Unit Voltage on any input pin with respect to Ground Parameter -0.5 to +4.6 V Storage temperature -65 to +125 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ TDV Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B) 150 2 °C KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Operating Conditions Symbol VDD Parameter Supply Voltage with respect to Ground TA Operating temperature Commercial TJ Junction temperature Commercial θJC Thermal Resistance TSSOP Min Typ Max Unit 3.0 3.3 3.6 V +70 °C 79.80 °C 0 TSSOP 124 °C/W P2042A DC Electrical Characteristics Symbol Parameter Min VIL Input low voltage VIH Input high voltage Input low current (pull-up resistor on inputs CP0, CP1 and SR0) Input high current (pull-down resistor on input SSON#) IIL IIH VOL Output low voltage ( IOL = 8mA) VOH Output high voltage ( IOH = -8mA) IDD Static supply current (CLKIN pulled LOW) Typ Unit 0.8 V 2.0 VDD + 0.3 V -50 µA 50 µA 0.4 V 2.5 ICC Dynamic supply current (3.3V and 10pF loading) VDD Operating voltage tON Power-up time (first locked cycle after power up) ZOUT Max VSS - 0.3 V 300 µA 6 15 22 mA 3.0 3.3 3.6 V 3 mS Clock output impedance Ω 35 AC Electrical Characteristics Symbol Min Typ Max Unit Input Clock frequency 30 74 110 MHz fOUT Output Clock frequency 30 74 110 MHz 1 tLH Output rise time (measured between 20% to 80%) 1.1 1.5 2 nS Output fall time (measured between 80% to 20%) 0.8 1.2 1.8 nS fIN tHL 1 Parameter tJC Jitter (cycle-to-cycle) tD Output duty cycle Note: 1. tLH and tHL are measured into a capacitive load of 10pF