P5P2304AF-1H08SR

ASM5P2304A 3.3 V Zero Delay Buffer Description ASM5P2304A is a versatile, 3.3 V zero−delay buffer designed to distribute high−speed clocks in PC, workstation, datacom, telecom and other high−performance applications. It is available in 8−pin package. The part has an on−chip PLL which locks to an input clock presented on the REF. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input−to−output propagation delay is guaranteed to be less than ±250 pS, and the output−to−output skew is guaranteed to be less than 200 pS. ASM5P2304A has two banks of two outputs each. Multiple ASM5P2304A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 500 pS. ASM5P2304A is available in two different configurations. Refer to ASM5P2304A Configurations Table. The ASM5P2304A−1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P2304A−1H is the high−drive version of the −1 and the rise and fall times on this device are faster. ASM5P2304A−2 allows the user to obtain REF and 1/2x or 2x frequencies on each output bank. The exact configuration and output frequencies depend on which output drives the feedback pin. http://onsemi.com SOIC−8 S SUFFIX CASE 751BD PIN CONFIGURATION 1 REF FBK CLKA1 VDD CLKA2 CLKB2 CLKB1 GND (Top View) Features • Zero Input−Output Propagation Delay, Adjustable by Capacitive • • • • • • • • Load on FBK Input Multiple Configurations − Refer to ASM5P2304A Configurations Table Input Frequency Range: 10 MHz to 133 MHz − Multiple Low−skew Outputs − Output−Output Skew less than 200 pS − Device−Device Skew less than 500 pS − Two Banks of Two Outputs Each Less than 200 pS Cycle−to−Cycle Jitter (−1, −1H, −2, −2H) 8−pin SOIC Package 3.3 V Operation Commercial and Industrial Temperature Range Advanced 0.35 !! CMOS Technology These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2011 August, 2011 − Rev. 3 1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Publication Order Number: ASM5P2304A/D ASM5P2304A FBK CLKA1 PLL REF CLKA2 /2 Extra Divider (−2) CLKB1 CLKB2 Figure 1. Block Diagram Table 1. ASM5P2304A CONFIGURATIONS Device Feedback From Bank A Frequency Bank B Frequency ASM5P2304A (−1, 1H) Bank A or Bank B Reference Reference ASM5P2304A (−2, −2H) Bank A Reference Reference /2 ASM5P2304A (−2, −2H) Bank B 2 x Reference Reference Zero Delay and Skew Control For applications requiring zero input−output delay, all outputs must be equally loaded. REF−Input to CLKA / CLKB Delay (pS) 1500 1000 500 0 −30 −25 −20 −15 −10 −5 5 0 10 15 20 25 30 −500 −1000 −1500 Output Load Difference: FBK Load − CLKA/CLKB Load (pF) Figure 2. REF Input to CLKA/CLKB Delay vs. Difference in Loading between FBK Pin and CLKA/CLKB Pins For applications requiring zero input−output delay, all outputs including the one providing feedback should be equally loaded. If input−output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output−output skew, be sure to load outputs equally. To close the feedback loop of the ASM5P2304A, the FBK pin can be driven from any of the four available clock outputs. The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input−output delay. This is shown in the above graph. http://onsemi.com 2 ASM5P2304A Table 2. PIN DESCRIPTION Pin # Pin Name Description 1 REF (Note 1) 2 CLKA1 (Note 2) Buffered clock output, bank A 3 CLKA2 (Note 2) Buffered clock output, bank A 4 GND 5 CLKB1 (Note 2) Buffered clock output, bank B 6 CLKB2 (Note 2) Buffered clock output, bank B 7 VDD 3.3 V supply 8 FBK PLL feedback input Input reference clock frequency, 5 V tolerant input Ground 1. Weak pull−down. 2. Weak pull−down on all outputs. Table 3. ABSOLUTE MAXIMUM RATINGS Parameter Min Max Unit Supply Voltage to Ground Potential −0.5 +4.6 V DC Input Voltage (Except REF) −0.5 VDD + 0.5 V DC Input Voltage (REF) −0.5 7 V Storage Temperature −65 +150 °C Max. Soldering Temperature (10 sec) 260 °C Junction Temperature 150 °C Static Discharge Voltage (As per JEDEC STD22− A114−B) 2000 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 3 ASM5P2304A Table 4. OPERATING CONDITIONS Parameter VDD TA Description Supply Voltage Operating Temperature (Ambient Temperature) Commercial temperature Industrial temperature Min Max Unit 3.0 3.6 V 0 70 °C −40 85 CL Load Capacitance, below 100 MHz 30 pF CL Load Capacitance, from 100 MHz to 133 MHz 15 pF CIN Input Capacitance (Note 3) 7 pF Max Unit 0.8 V 3. Applies to both Ref Clock and FBK. Table 5. ELECTRICAL CHARACTERISTICS Parameter Description Test Conditions Min VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current VIN = 0 V 50 !!A IIH Input HIGH Current VIN = VDD 100 !!A VOL Output LOW Voltage (Note 4) IOL = 8 mA (−1, −2) IOL = 12 mA (−1H, −2H) 0.4 V VOH Output HIGH Voltage (Note 4) IOH = −8 mA (−1, −2) IOH = −12 mA (−1H, −2H) IDD Supply Current Unloaded outputs @ 100 MHz 2.2 V 2.4 V Commercial temp. 35 Industrial temp. 40 Unloaded outputs @ 66 MHz, (−1, −1H, −2, −2H) Commercial temp. 25 Industrial temp. 30 Unloaded outputs @ 33 MHz, (−1, −1H, −2, −2H) Commercial temp. 16 Industrial temp. 20 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. http://onsemi.com 4 mA ASM5P2304A Table 6. SWITCHING CHARACTERISTICS (Notes 5, 6) Parameter Test Conditions Output Frequency 30 pF load 15 pF load Min Typ Max Unit MHz (−1, −1H) devices 10 100 (−2, −2H) devices 12 100 (−1, −1H) devices 10 133 (−2, −2H) devices 12 133 Duty Cycle (Note 7) (−1, −2, −1H, −2H) Measured at 1.4 V, FOUT < 66.66 MHz, 30 pF load 40 50 60 % Duty Cycle (Note 7) (−1, −2,−1H, −2H) Measured at 1.4 V, FOUT ≤ 50 MHz, 15 pF load 45 50 55 % Output Rise Time (Note 7) (−1, −2) Measured between 0.8 V and 2.0 V, 30 pF load Commercial temp. 2.2 nS Industrial temp. 2.5 Output Rise Time (Note 7) (−1H, −2H) Measured between 0.8 V and 2.0 V, 30 pF load Output Rise Time (Note 7) (−1, −2) Measured between 0.8 V and 2.0 V, 15 pF load Output Fall Time (Note 7) (−1, −2) Measured between 2.0 V and 0.8 V, 30 pF load Commercial temp. Output Fall Time (Note 7) (−1H, −2H) Measured between 2.0 V and 0.8 V, 30 pF load Commercial temp., Industrial temp. Output Fall Time (Note 7) (−1, −2) Commercial temp., Industrial temp. 1.5 Industrial temp. 2 nS 1.5 nS 2.2 nS 2.5 1.5 nS Measured between 2.0 V and 0.8 V, 15 pF load 1.5 nS Output−to−output skew on same bank (−1, −1H, −2, −2H) (Note 7) All outputs equally loaded 200 pS Output bank A −to− output bank B skew (−1, −1H) All outputs equally loaded 200 Output bank A to output Bank B skew (−2, −2H) (Note 7) All outputs equally loaded 400 Delay, REF Rising Edge to FBK Rising Edge (Note 7) Measured at VDD /2 0 ±250 pS Device−to−Device Skew (Note 7) Measured at VDD/2 on the FBK pins of the device 0 500 pS Measured at 66.67 MHz, loaded outputs, 15 pF load 180 pS Measured at 66.67 MHz, loaded outputs, 30 pF load 200 Measured at 133 MHz, loaded outputs, 15 pF load 125 Measured at 66.67 MHz, loaded outputs, 15 pF load 380 Measured at 66.67 MHz, loaded outputs, 30 pF load 400 Stable power supply, valid clock presented on REF and FBK pins 1.0 Cycle−to−Cycle Jitter (Note 7) (−1, −1H) (−2, −2H) PLL Lock Time (Note 7) 5. For all measurements use Test Circuit #1. 6. All parameters are specified at Commercial and Industrial temperature unless stated otherwise. 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. http://onsemi.com 5 1.25 mS ASM5P2304A Switching Waveforms t1 t2 1.4 V 1.4 V 1.4 V OUTPUT Figure 3. Duty Cycle Timing 2V 2V 0.8 V VDD 0.8 V OUTPUT 0V t4 t3 Figure 4. All Outputs Rise/Fall Time 1.4 V OUTPUT 1.4 V OUTPUT t5 Figure 5. Output−Output Skew VDD/2 INPUT VDD/2 FBK t6 Figure 6. Input−Output Propagation Delay VDD/2 FBK, Device1 VDD/2 FBK, Device2 t7 Figure 7. Device−Device Skew TEST CIRCUIT #1 22 Q FBK CLK A / CLK B +3.3 V CLOAD VDD 0.1 !!F ASM5P2304A 22 Q CLK A / CLK B GND CLOAD Figure 8. Test Circuit http://onsemi.com 6 ASM5P2304A PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 MAX c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 e PIN # 1 IDENTIFICATION NOM 4.00 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 7 ASM5P2304A Table 7. ORDERING INFORMATION Part Number Marking P5P2304AF−1−08SR 5P2304AF−1 ASM5P2304AF−1−08−ST ASM5I2304AF−1−08−SR ASM5I2304AF−1−08−ST Package Type Temperature 8−pin 150−mil SOIC−TAPE & REEL, Pb free Commercial 5P2304AF−1 8−pin 150−mil SOIC−TUBE, Pb free Commercial 5I2304AF−1 8−pin 150−mil SOIC−TAPE & REEL, Pb free Industrial 5I2304AF−1 8−pin 150−mil SOIC−TUBE, Pb free Industrial P5P2304AF−1H08SR 5P2304AF−1H 8−pin 150−mil SOIC−TAPE & REEL, Pb free Commercial ASM5P2304AF−1H−08−ST 5P2304AF−1H 8−pin 150−mil SOIC−TUBE, Pb free Commercial P5I2304AF−1H08SR 5I2304AF−1H 8−pin 150−mil SOIC−TAPE & REEL, Pb free ASM5I2304AF−1H−08−ST 5I2304AF−1H 8−pin 150−mil SOIC−TUBE, Pb free P5P2304AF−2−08SR 5P2304AF−2 8−pin 150−mil SOIC−TAPE & REEL, Pb free Commercial P5P2304AF−2−08ST 5P2304AF−2 8−pin 150−mil SOIC−TUBE, Pb free, Pb free Commercial ASM5I2304AF−2−08−SR 5I2304AF−2 8−pin 150−mil SOIC−TAPE & REEL, Pb free Industrial P5I2304AF−2−08ST 5I2304AF−2 8−pin 150−mil SOIC−TUBE, Pb free Industrial ASM5P2304AF−2H−08−SR 5P2304AF−2H ASM5P2304AF−2H−08−ST ASM5I2304AF−2H−08−SR ASM5I2304AF−2H−08−ST Industrial Industrial 8−pin 150−mil SOIC−TAPE & REEL, Pb free Commercial 5P2304AF−2H 8−pin 150−mil SOIC−TUBE, Pb free Commercial 5I2304AF−2H 8−pin 150−mil SOIC−TAPE & REEL, Pb free Industrial 5I2304AF−2H 8−pin 150−mil SOIC−TUBE, Pb free Industrial ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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