ASM5P2308A
3.3 V Zero-Delay Buffer
Description
ASM5P2308A is a versatile, 3.3 V zero−delay buffer designed to
distribute high−speed clocks. It is available in a 16−pin package. The
part has an on−chip PLL which locks to an input clock presented on
the REF pin. The PLL feedback is required to be driven to FBK pin,
and can be obtained from one of the outputs. The input−to−output
propagation delay is guaranteed to be less than ±250 pS, and the
output−to−output skew is guaranteed to be less than 200 pS.
The ASM5P2308A has two banks of four outputs each, which can
be controlled by the select inputs as shown in the Select Input
Decoding Table. If all the output clocks are not required, Bank B can
be three−stated. The select input also allows the input clock to be
directly applied to the outputs for chip and system testing purposes.
Multiple ASM5P2308A devices can accept the same input clock
and distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 pS.
ASM5P2308A is available in five different configurations. Refer to
ASM5P2308A Configurations Table. The ASM5P2308A−1 is the base
part, where the output frequencies equal the reference clock input. The
ASM5P2308A−1H is the high−drive version of the −1 and the rise and
fall times on this device are faster.
ASM5P2308A−2 allows the user to obtain 2x and 1x frequencies on
each output bank. The exact configuration and output frequencies
depends on which output drives the feedback pin. ASM5P2308A−3
allows the user to obtain 4x and 2x frequencies on the outputs.
ASM5P2308A−4 enables the user to obtain 2x clocks on all outputs.
The ASM5P2308A−5H is a high−drive version with REF/2 output
on both banks.
ASM5P2308A is an extremely versatile part, and can be used in a
variety of applications.
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TSSOP−16
T SUFFIX
CASE 948AN
SOIC−16
S SUFFIX
CASE 751BG
PIN CONFIGURATION
1
FBK
REF
CLKA1
CLKA4
CLKA2
CLKA3
VDD
VDD
GND
GND
CLKB1
CLKB4
CLKB2
CLKB3
S2
S1
(Top View)
Features
• Zero Input−output Propagation Delay, Adjustable by Capacitive Load
on FBK Input
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
• Multiple Configurations –
•
•
•
•
•
•
•
Refer to ASM5P2308A Configurations Table
Input Frequency Range: 10 MHz to 133 MHz
Multiple Low−skew Outputs
♦ Output−output Skew less than 200 pS
♦ Device−device Skew less than 700 pS
♦ Two Banks of Four Outputs Each,
Three−state by Two Select Inputs
Less than 200 pS Cycle−to−Cycle Jitter (−1, −1H, −2, −3, −4, −5H)
16−pin SOIC and TSSOP Packages
3.3 V Operation
Commercial and Industrial Temperature Range
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 3
1
Publication Order Number:
ASM5P2308A/D
ASM5P2308A
FBK
/2
REF
MUX
PLL
/2
CLKA1
Extra Divider (−5H)
Extra Divider (−3, −4)
CLKA2
CLKA3
CLKA4
S2
Select
Input
Decoding
/2
S1
CLKB1
CLKB2
Extra Divider (−2, −3)
CLKB3
CLKB4
Figure 1. Block Diagram
Table 1. SELECT INPUT DECODING FOR ASM5P2308A
S2
S1
Clock A1 − A4
Clock B1 − B4
Output Source
PLL Shut−Down
0
0
Three−state
Three−state
PLL
Y
0
1
Driven
Three−state
PLL
N
1
0
Driven (Note 1)
Driven
Reference
Y
1
1
Driven
Driven
PLL
N
1. Outputs are non−inverted on 2308A−2 and 2308A−3 in bypass mode, S2 = 1 and S1 = 0.
Table 2. ASM5P2308A CONFIGURATIONS (This table is applicable when PLL is not Shut Down.)
Device
Feedback From
Bank A Frequency
Bank B Frequency
ASM5P2308A (−1, −1H)
Bank A or Bank B
Reference
Reference
ASM5P2308A−2
Bank A
Reference
Reference /2
ASM5P2308A−2
Bank B
2 X Reference
Reference
ASM5P2308A−3
Bank A
2 X Reference
Reference or Reference (Note 2)
ASM5P2308A−3
Bank B
4 X Reference
2 X Reference
ASM5P2308A−4
Bank A or Bank B
2 X Reference
2 X Reference
ASM5P2308A−5H
Bank A or Bank B
Reference /2
Reference /2
2. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the ASM5P2308A−2.
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2
ASM5P2308A
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay between input and output.
REF−Input to CLKA / CLKB Delay (pS)
1500
1000
500
0
−30 −25
−20
−15
−10
−5
5
0
10
15
20
25
30
−500
−1000
−1500
Figure 2. Output Load Difference: FBK Load − CLKA/CLKB Load (pF)
For applications requiring zero input−output delay, all
outputs including the one providing feedback should be
equally loaded. If input−output delay adjustments are
required, use the above graph to calculate loading
differences between the feedback output and remaining
outputs. For zero output−output skew, be sure to load outputs
equally.
To close the feedback loop of the ASM5P2308A, the FBK
can be driven from any of the eight available clock outputs.
The output driving the FBK pin will be driving a total load
of 7 pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining outputs)
can adjust the input−output delay. This is shown in the above
graph.
Table 3. PIN DESCRIPTION FOR ASM5P2308A
Pin #
Pin Name
Description
1
REF (Note 3)
2
CLKA1 (Note 4)
3
CLKA2 (Note 4)
4
VDD
3.3 V supply
5
GND
Ground
6
CLKB1 (Note 4)
Buffered clock output, bank B
7
CLKB2 (Note 4)
Buffered clock output, bank B
8
S2 (Note 5)
Input reference clock frequency, 5 V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
Select input, bit 2
9
S1 (Note 5)
10
CLKB3 (Note 4)
Buffered clock output, bank B
Select input, bit 1
11
CLKB4 (Note 4)
Buffered clock output, bank B
12
GND
Ground
13
VDD
3.3 V supply
14
CLKA3 (Note 4)
15
CLKA4 (Note 4)
16
FBK
Buffered clock output, bank A
Buffered clock output, bank A
PLL feedback input
3. Weak pull−down.
4. Weak pull−down on all outputs.
5. Weak pull−up on these inputs.
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ASM5P2308A
Table 4. ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
−0.5
+4.6
V
DC Input Voltage (Except REF)
−0.5
VDD + 0.5
V
DC Input Voltage (REF)
−0.5
7
V
Storage Temperature
−65
+150
°C
Max. Soldering Temperature (10 sec)
260
°C
Junction Temperature
150
°C
2000
V
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. OPERATING CONDITIONS
Parameter
VDD
TA
Description
Supply Voltage
Operating Temperature
(Ambient Temperature)
Commercial temperature
Industrial temperature
Min
Max
Unit
3.0
3.6
V
0
70
°C
−40
85
CL
Load Capacitance, below 100 MHz
30
pF
CL
Load Capacitance, from 100 MHz to 133 MHz
15
pF
CIN
Input Capacitance (Note 6)
7
pF
6. Applies to both Ref Clock and FBK.
Table 6. ELECTRICAL CHARACTERISTICS
Parameter
Description
Test Conditions
Min
Max
Unit
0.8
V
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0 V
50
�-tA
IIH
Input HIGH Current
VIN = VDD
100
�-tA
VOL
Output LOW Voltage
(Note 7)
IOL = 8 mA (−1, −2, −3, −4)
IOL = 12 mA (−1H, −5H)
0.4
V
VOH
Output HIGH Voltage
(Note 7)
IOH = −8 mA (−1, −2, −3, −4)
IOH = −12 mA (−1H, −5H)
IDD
Supply Current
(Note 8)
Unloaded outputs at 100 MHz,
Select inputs at VDD or GND
(−1, −1H, −2,−3,−4)
Commercial temp.
40
Industrial temp.
45
Unloaded outputs; 100 MHz
REF, Select inputs at VDD or
GND (−5H)
Commercial temp.
30
Industrial temp.
35
Unloaded outputs at 66 MHz
Commercial temp.
32
Industrial temp.
34
Commercial temp.
18
Industrial temp.
20
2.2
Unloaded outputs at 33 MHz
4
V
2.4
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. Supply Currents are measured for PLL−Driven Mode (S2 = 1, S1 = 1).
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V
mA
ASM5P2308A
Table 7. SWITCHING CHARACTERISTICS (For all measurements use Test Circuit #1.) (Note 9)
Parameter
Output Frequency
(Refer to ASM5P2308A
Configurations Table)
Test Conditions
30 pF load
15 pF load
Min
Typ
Max
Unit
MHz
( −1, −1H)
10
100
(−2)
12
100
(−3)
15
100
(−4)
20
100
(−5H)
5
66.67
( −1, −1H)
10
133
(−2)
12
133
(−3)
15
133
(−4)
20
133
MHz
Duty Cycle (Note 10)
(−1, −2, −3, −4, −1H, −5H)
Measured at 1.4 V, FOUT ≤ 66.66 MHz, 30 pF load
40
50
60
%
Duty Cycle (Note 10)
(−1, −2, −3, −4, −1H, −5H)
Measured at 1.4 V, FOUT ≤ 50 MHz, 15 pF load
45
50
55
%
Output Rise Time (Note 10)
(−1, −2, −3, −4)
Measured between 0.8 V
and 2.0 V, 30 pF load
Commercial temp.
2.2
nS
Industrial temp.
2.5
Output Rise Time (Note 10)
(−1, −2, −3, −4)
Measured between 0.8 V
and 2.0 V, 15 pF load
Commercial temp.,
Industrial temp.
1.5
nS
Output Rise Time (Note 10)
(−1H, −5H)
Measured between 0.8 V
and 2.0 V, 30 pF load
2
nS
Output Fall Time (Note 10)
(−1, −2, −3, −4)
Measured between 2.0 V
and 0.8 V, 30 pF load
Commercial temp.
2.2
nS
Industrial temp.
2.5
Output Fall Time (Note 10)
(−1, −2, −3, −4)
Measured between 2.0 V
and 0.8 V, 15 pF load
Commercial temp.,
Industrial temp.
1.5
nS
Output Fall Time (Note 10)
(−1H, −5H)
Measured between 2.0 V
and 0.8 V, 30 pF load
1.5
nS
1.5
1.25
Output−to−output skew on same bank (Note 10)
(−1, −2, −3, −4)
All outputs equally loaded
200
pS
Output−to−output skew (Note 10) (−1H, −5H)
All outputs equally loaded
200
pS
Output bank A −to− output Bank B skew (Note 10)
(−1, −4, −5H)
All outputs equally loaded
200
pS
400
pS
pS
Output bank A −to− output
Bank B skew (Note 10) (−2, −3)
All outputs equally loaded
Delay, REF Rising Edge to FBK
Rising Edge (Notes 10, 11)
Measured at VDD /2
0
±250
Device−to−Device Skew
(Note 10)
Measured at VDD/2 on the FBK pins of the device
0
700
Cycle−to−Cycle Jitter (Note 10)
(−1, −1H, −4, −5H)
Measured at 66.67 MHz, loaded outputs, 15 pF load
200
Measured at 66.67 MHz, loaded outputs, 30 pF load
200
Measured at 133.3 MHz, loaded outputs, 15 pF load
(Note 12)
125
Measured at 66.67 MHz, loaded outputs, 15 pF load
400
Cycle−to−Cycle Jitter (Note 10)
(−2, −3)
PLL Lock Time (Note 10)
Measured at 66.67 MHz, loaded outputs, 30 pF load
Stable power supply, valid clock presented on REF and
FBK pins
9. All parameters are specified at Commercial and Industrial temperature unless stated otherwise.
10. Parameter is guaranteed by design and characterization. Not 100% tested in production.
11. Refer to Test Circuit #2 *Not applicable for (−1, −2, −1H, −2H).
12. Not applicable for −5H.
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5
1.0
mS
ASM5P2308A
Switching Waveforms
t1
t2
1.4 V
1.4 V
1.4 V
OUTPUT
Figure 3. Duty Cycle Timing
2V
2V
0.8 V
VDD
0.8 V
OUTPUT
0V
t4
t3
Figure 4. All Outputs Rise/Fall Time
1.4 V
OUTPUT
1.4 V
OUTPUT
t5
Figure 5. Output−Output Skew
VDD/2
INPUT
VDD/2
FBK
t6
Figure 6. Input−Output Propagation Delay
VDD/2
FBK, Device1
VDD/2
FBK, Device2
t7
Figure 7. Device−Device Skew
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ASM5P2308A
TEST CIRCUIT #1
22 Q
FBK
+3.3 V
CLK A / CLK B
2
CLOAD
VDD
0.1 �-tF
ASM5P2308A
22 Q
CLK A / CLK B
GND
2
CLOAD
TEST CIRCUIT #2
FBK
22 Q
ASM5P2308A
22 Q
CLK A / CLK B
+3.3 V
2
0.1 �-tF
VDD
CLK A / CLK B
GND
8.2 pF (Note 13)
2
Figure 8. Test Circuits
13. Refer to Test Circuit #2 *Not applicable for (-1, -2, -1H, -2H).
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ASM5P2308A
PACKAGE DIMENSIONS
SOIC−16, 150 mils
CASE 751BG−01
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
D
9.80
MAX
0.25
9.90
10.00
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
e
PIN#1 IDENTIFICATION
NOM
1.27 BSC
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
8
A
e
b
c
L
A1
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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ASM5P2308A
PACKAGE DIMENSIONS
TSSOP16, 4.4x5
CASE 948AN−01
ISSUE O
b
SYMBOL
MIN
NOM
A
A1
MAX
1.10
0.05
0.15
A2
0.85
0.95
b
0.19
0.30
c
0.13
0.20
D
4.90
5.10
E
6.30
6.50
E1
4.30
4.50
E1 E
e
0.65 BSC
L
1.00 REF
L1
0.45
0.75
θ
0º
8º
e
PIN#1
IDENTIFICATION
TOP VIEW
D
A2 A
c
θ1
A1
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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9
L
ASM5P2308A
Table 8. ORDERING INFORMATION
Part Number
ASM5P2308AF−1−16−ST
Marking
Package Type
5P2308AF−1
16−pin 150−mil SOIC−TUBE, Pb free
ASM5I2308AF−1−16−ST
5I2308AF−1
16−pin 150−mil SOIC−TUBE, Pb free
ASM5P2308AF−1−16−SR
5P2308AF−1
16−pin 150−mil SOIC−TAPE & REEL, Pb free
ASM5I2308AF−1−16−SR
5I2308AF−1
16−pin 150−mil SOIC−TAPE & REEL, Pb free
ASM5P2308AF−1−16−TT
5P2308AF−1
16−PIN 150−mil TSSOP − TUBE, Pb free
ASM5I2308AF−1−16−TT
5I2308AF−1
16−PIN 150−mil TSSOP − TUBE, Pb free
ASM5P2308AF−1−16−TR
5P2308AF−1
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free
5I2308AF−1
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free
ASM5I2308AF−1−16−TR
P5P2308AF−1H16ST
5P2308AF−1H
16−pin 150−mil SOIC−TUBE, Pb free
ASM5I2308AF−1H−16−ST
5I2308AF−1H
16−pin 150−mil SOIC−TUBE, Pb free
P5P2308AF−1H16SR
5P2308AF−1H
16−pin 150−mil SOIC−TAPE & REEL, Pb free
ASM5I2308AF−1H−16−SR
5I2308AF−1H
16−pin 150−mil SOIC−TAPE & REEL, Pb free
ASM5P2308AF−1H−16−TT
5P2308AF−1H
16−PIN 150−mil TSSOP − TUBE, Pb free
ASM5I2308AF−1H−16−TT
5I2308AF−1H
16−PIN 150−mil TSSOP − TUBE, Pb free
P5P2308AF−1H16TR
5P2308AF−1H
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free
ASM5I2308AF−1H−16−TR
5I2308AF−1H
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free
P5P2308AF−2−16ST
5P2308AF−2
16−pin 150−mil SOIC−TUBE, Pb free
ASM5I2308AF−2−16−ST
5I2308AF−2
16−pin 150−mil SOIC− TUBE, Pb free
P5P2308AF−216SR
5P2308AF−2
16−pin 150−mil SOIC−TAPE & REEL, Pb free
ASM5I2308AF−2−16−SR
5I2308AF−2
16−pin 150−mil SOIC−TAPE & REEL, Pb free
ASM5P2308AF−2−16−TT
5P2308AF−2
16−PIN 150−mil TSSOP − TUBE, Pb free
P5I2308AF−216TT
5I2308AF−2
16−PIN 150−mil TSSOP − TUBE, Pb free
P5P2308AF−216TR
5P2308AF−2
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free
ASM5I2308AF−2−16−TR
5I2308AF−2
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free
ASM5P2308AF−3−16−ST
5P2308AF−3
16−pin 150−mil SOIC−TUBE, Pb free
ASM5I2308AF−3−16−ST
5I2308AF−3
16−pin 150−mil SOIC− TUBE, Pb free
ASM5P2308AF−3−16−SR
5P2308AF−3
16−pin 150−mil SOIC−TAPE & REEL, Pb free
ASM5I2308AF−3−16−SR
5I2308AF−3
16−pin 150−mil SOIC−TAPE & REEL, Pb free
ASM5P2308AF−3−16−TT
5P2308AF−3
16−PIN 150−mil TSSOP − TUBE, Pb free
ASM5I2308AF−3−16−TT
5I2308AF−3
16−PIN 150−mil TSSOP − TUBE, Pb free
P5P2308AF−3−16TR
5P2308AF−3
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free
ASM5I2308AF−3−16−TR
5I2308AF−3
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free
ASM5P2308AF−4−16−ST
5P2308AF−4
16−pin 150−mil SOIC−TUBE, Pb free
ASM5I2308AF−4−16−ST
5I2308AF−4
16−pin 150−mil SOIC− TUBE, Pb free
ASM5P2308AF−4−16−SR
5P2308AF−4
16−pin 150−mil SOIC−TAPE & REEL, Pb free
ASM5I2308AF−4−16−SR
5I2308AF−4
16−pin 150−mil SOIC−TAPE & REEL, Pb free
ASM5P2308AF−4−16−TT
5P2308AF−4
16−PIN 150−mil TSSOP − TUBE, Pb free
ASM5I2308AF−4−16−TT
5I2308AF−4
16−PIN 150−mil TSSOP − TUBE, Pb free
ASM5P2308AF−4−16−TR
5P2308AF−4
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free
5I2308AF−4
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free
ASM5I2308AF−4−16−TR
Temperature
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
ASM5P2308AF−5H−16−ST
5P2308AF−5H
16−pin 150−mil SOIC−TUBE, Pb free
Commercial
ASM5I2308AF−5H−16−ST
5I2308AF−5H
16−pin 150−mil SOIC− TUBE, Pb free
Industrial
ASM5P2308AF−5H−16−SR
5P2308AF−5H
16−pin 150−mil SOIC−TAPE & REEL, Pb free
ASM5I2308AF−5H−16−SR
5I2308AF−5H
16−pin 150−mil SOIC−TAPE & REEL, Pb free
ASM5P2308AF−5H−16−TT
5P2308AF−5H
16−PIN 150−mil TSSOP − TUBE, Pb free
Commercial
ASM5I2308AF−5H−16−TT
5I2308AF−5H
16−PIN 150−mil TSSOP − TUBE, Pb free
Industrial
ASM5P2308AF−5H−16−TR
5P2308AF−5H
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free
Commercial
ASM5I2308AF−5H−16−TR
5I2308AF−5H
16−PIN 150−mil TSSOP − TAPE & REEL, Pb free
Industrial
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Commercial
Industrial
ASM5P2308A
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
11
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
ASM5P2308A/D
