PACSZ1284
IEEE 1284 Parallel Port
ESD/EMI/Termination
Network
Product Description
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The PACSZ1284 combines EMI filtering, ESD protection, and
signal termination in a single QSOP package for parallel port
interfaces complying to the IEEE 1284 standard.
The PACSZ1284 provides a complete parallel port termination
solution. It integrates the equivalent of 60 discrete components,
making it ideal for space critical applications. The pins of the device
which connect to the parallel port are protected to 30 kV contact
discharge, well beyond Level 4 of the IEC 61000−4−2 specification.
All other pins are ESD−protected for contact discharges up to 8 kV
per IEC 61000−4−2.
There are two values available for pull−up resistor R1. For the
PACSZ1284−02, R1 = 2.2 kW; for the PACSZ1284−04, R1 = 4.7 kW.
The PACSZ1284 is housed in a 28−pin QSOP package and is
available with RoHS compliant lead−free finishing.
QSOP−28
QR SUFFIX
CASE 492AA
MARKING DIAGRAM
PACSZ1284 02QR
Features
17 EMI Filters
17 ESD Protectors Yielding Protection to 30 kV Contact
PACSZ1284 02QR
Discharge, per IEC 61000−4−2 Specification
17 Terminators with Choice of Resistor Values
28−Pin QSOP Package
These Devices are Pb−Free and are RoHS Compliant
= Specific Device Code
PACSZ128404QR
PACSZ128404QR
Applications
Parallel Ports of PCs, Printers, Peripherals, and Set−Top Boxes
= Specific Device Code
ORDERING INFORMATION
Device
Package
Shipping†
PACSZ1284−02QR QSOP−28 2500/Tape & Reel
(Pb−Free)
PACSZ1284−04QR QSOP−28 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 4
1
Publication Order Number:
PACSZ1284/D
PACSZ1284
ELECTRICAL SCHEMATIC
28
R1
27
R1
R1
26
R1
25
R1
R1
R2
C
C
C
1
C
2
24
C
R1
R2
C
3
23
22 21
R1
R1
R2
C
5
R1
7
C
8
R1
16
R1
R2
C
9
17
R1
R2
C
6
R1 = 4.7 kW
R2 = 33 W
C = 150 pF
18
R1
R2
C
PACSZ1284−04
R1 = 2.2 kW
R2 = 33 W
C = 150 pF
19
R1
R2
C
4
20
PACSZ1284−02
C
10
R1
R2
C
11
C
12
15
R1
R2
C
13
C
14
PACKAGE / PINOUT DIAGRAMS
CAP−FILTERED
1
28
CAP−FILTERED
CAP−FILTERED
2
27
CAP−FILTERED
SUPERCHIP SIDE SERIES−TERMINATED
3
26
CONNECTOR SIDE SERIES−TERMINATED
SUPERCHIP SIDE SERIES−TERMINATED
4
25
CONNECTOR SIDE SERIES−TERMINATED
SUPERCHIP SIDE SERIES−TERMINATED
5
24
CONNECTOR SIDE SERIES−TERMINATED
SUPERCHIP SIDE SERIES−TERMINATED
6
23
CONNECTOR SIDE SERIES−TERMINATED
SUPERCHIP SIDE SERIES−TERMINATED
7
22
GND
CAP−FILTERED
8
21
CONNECTOR SIDE SERIES−TERMINATED
SUPERCHIP SIDE SERIES−TERMINATED
9
20
VCC
CAP−FILTERED
10
19
CONNECTOR SIDE SERIES−TERMINATED
SUPERCHIP SIDE SERIES−TERMINATED
11
18
CONNECTOR SIDE SERIES−TERMINATED
CAP−FILTERED
12
17
CONNECTOR SIDE SERIES−TERMINATED
SUPERCHIP SIDE SERIES−TERMINATED
13
16
CONNECTOR SIDE SERIES−TERMINATED
SUPERCHIP SIDE SERIES−TERMINATED
14
15
CAP−FILTERED
28−Pin QSOP
Table 1. PIN DESCRIPTIONS
Leads
Name
1, 2, 8, 10, 12, 15, 27, 28
Capacitor−Filtered
Description
3−7, 9, 11, 13, 14
Super I/O Chip Side Series−Terminated
IEEE 1284 Signals on the Super I/O Chip Side which Require
Series Termination
16−19, 21, 23−26
Parallel Port
Connector Side Series−Terminated
IEEE 1284 Signals on the Parallel Port Connector Side which
Require Series Termination
20
VCC
Supply Rail for the Device
22
GND
Ground Reference for the Device
IEEE 1284 Signals which Require No Series Termination
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2
PACSZ1284
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
5.5
V
Input Voltage Range, No Clamping
−0.4 to 5.5
V
Storage Temperature Range
−40 to +150
C
Power Dissipation per Resistor
0.1
W
Package Power Dissipation
1.0
W
VCC Voltage
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
VCC Voltage
Operating Temperature
Rating
Units
5.0
V
−40 to +85
C
Table 4. ELECTRICAL OPERATING CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TOLR
Absolute Resistance Tolerance
Measured at TA = 25C
20
%
TOLC
Absolute Capacitance Tolerance
Measured at 1 MHz, 2.5 VDC,
TA = 25C
20
%
ILEAK
Leakage Current to GND
Measured at 5.0 VDC, TA = 25C
10
mA
VESDi
ESD Protection, Input Pins
Pins 3, 4, 5, 6, 7, 9, 11, 13, & 14,
per IEC 61000−4−2 Specification
(Notes 1 and 2)
8
kV
VESD
ESD Protection, Connector Pins
Pins 1, 2, 8, 10, 12, 15, 16, 17, 18, 19,
21, 23, 24, 25, 26, 27, & 28,
per IEC 61000−4−2 Specification
(Notes 1 and 3)
30
kV
Clamping Voltage under ESD Discharge
ESD Applied to Connector Pin,
Measured at Corresponding Input Pin;
+8 kV Discharge, Human Body Model
(Note 1)
8.3
V
ESD Applied to Connector Pin,
Measured at Corresponding Input Pin;
−8 kV Discharge, Human Body Model
(Note 1)
−2.7
V
VCLAMP
1. ESD voltage applied between Input/Connector pins and ground, one pin at a time.
2. Pins 3−7, 9, 11, 13, and 14 typically connect to the I/O pins of a Super I/O chip.
3. Pins 1, 2, 8, 10, 12, 15−19, 21, and 23−28 typically connect to the Parallel Port connector.
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3
1
PACSZ1284
PERFORMANCE INFORMATION
Filter Capacitors
The IEEE 1284 specification requires both termination and EMI filtering on a total of 17 lines. Basic filtering is provided
through the presence of a capacitor on all signal lines. The filter capacitor is the junction capacitance of an ESD diode. The
typical capacitance at a reverse voltage of 2.5 V is 150 pF. This diode capacitance is somewhat voltage dependent. See Figure 1.
Figure 1. Diode Capacitance vs. Reverse Voltage
The higher speed Data and Strobe lines (9 in total) require an additional series resistor termination for proper operation, while
the eight (8) Status lines do not. See Table 5.
Filter Insertion Loss
Figure 2 shows the typical Insertion Loss graphs of the PACSZ1284 for Data and Strobe signals. The curves are dependent
on the physical location of the filter elements with respect to the ground terminal of this device. These graphs are measured
in a 50 W environment on a Hewlett Packard HP 8753C Analyzer. The signal source is introduced at the resistor input and the
output is measured at the corresponding protection diode. The actual pins measured are labeled in the Figure 2 graph.
Figure 2. Typical Filter Insertion Loss
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4
PACSZ1284
APPLICATION INFORMATION
Termination Considerations
The IEEE 1284 specification requires both termination and EMI filtering on a total of 17 signal lines. Control and Status
lines (8 in total) only require a pull−up resistor and a filter capacitor. The Data lines and Strobe also require a series termination
resistor in addition to the pull−up resistors and filter capacitors. See Table 5, in conjunction with the schematic diagram on
page 2.
Table 5. IEEE 1284 TERMINATION REQUIREMENTS
Signal Termination Requirements
Signal Name
Series Termination
Data1 − Data8
Yes
Strobe
Yes
Init
Not Required
AutoFeedXT
Not Required
Selectin
Not Required
ACK
Not Required
Busy
Not Required
Paper Empty
Not Required
Select
Not Required
Fault
Not Required
Interfacing to IEEE 1284 Connectors
IEEE 1284 defines three interface connectors:
1284 A is a 25−pin DB series connector which is the de facto PC standard for the host connection
1284 B is a 36−pin, 0.085 inch centerline connector used on the peripheral device
1284 C is a new 36−pin, 0.050 inch centerline connector which can be used for both host and peripheral
Figure 3A shows a possible hook−up between the 1284−A connector on a PC motherboard and the PACSZ1284, illustrating
how the pin configuration of the PACSZ1284 allows for easy interconnect between the two. The dotted I/O signals of the
PACSZ1284 will typically be connected to a Super I/O chip on the motherboard.
Figure 3B shows a possible hook−up between the 1284−B connector on a peripheral and the PACSZ1284
Figure 3C shows a possible hook−up between the 1284−C connector and the PACSZ1284.
Figure 3. Example Connections of IEEE 1284 Connectors with PACSZ1284
Table 6 provides the IEEE 1284 signal assignments for the three connectors, and example PACSZ1284 pin connections.
When connecting a 1284−A host to a 1284−B peripheral, the “Peripheral Logic High” signal is not used. Similarly, when
a 1284−A host is connected to a 1284−C peripheral, the “Peripheral Logic High” and “Host Logic High” are not used. These
two signals are optionally used to detect a “Power Off” or “Cable Disconnect” state for host and peripheral, respectively.
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5
PACSZ1284
APPLICATION INFORMATION (Cont’d)
Table 6. IEEE 1284 CONNECTOR PINOUTS AND PACSZ1284 CONNECTION GUIDELINES
PACSZ1284
Pin Type
1284−A
25−Pin DSUB
1284−B
36−Pin Champ
1284−C
36−Pin High Density
Signal
Pin
Signal
Pin
Signal
Pin
P−Port Conn. Side, Series−Terminated (16−19, 21, or 23−26)
STROBE
1
STROBE
1
STROBE
15
P−Port Conn. Side, Series−Terminated (16−19, 21, or 23−26)
Data 1
2
Data 1
2
Data 1
6
P−Port Conn. Side, Series−Terminated (16−19, 21, or 23−26)
Data 2
3
Data 2
3
Data 2
7
P−Port Conn. Side, Series−Terminated (16−19, 21, or 23−26)
Data 3
4
Data 3
4
Data 3
8
P−Port Conn. Side, Series−Terminated (16−19, 21, or 23−26)
Data 4
5
Data 4
5
Data 4
9
P−Port Conn. Side, Series−Terminated (16−19, 21, or 23−26)
Data 5
6
Data 5
6
Data 5
10
P−Port Conn. Side, Series−Terminated (16−19, 21, or 23−26)
Data 6
7
Data 6
7
Data 6
11
P−Port Conn. Side, Series−Terminated (16−19, 21, or 23−26)
Data 7
8
Data 7
8
Data 7
12
P−Port Conn. Side, Series−Terminated (16−19, 21, or 23−26)
Data 8
9
Data 8
9
Data 8
13
Capacitor−Filtered (1, 2, 8, 10, 12, 15, 27, or 28)
ACK
10
ACK
10
ACK
3
Capacitor−Filtered (1, 2, 8, 10, 12, 15, 27, or 28)
BUSY
11
BUSY
11
BUSY
1
Capacitor−Filtered (1, 2, 8, 10, 12, 15, 27, or 28)
PError
12
PError
12
PError
5
Capacitor−Filtered (1, 2, 8, 10, 12, 15, 27, or 28)
Select
13
Select
13
Select
2
Capacitor−Filtered (1, 2, 8, 10, 12, 15, 27, or 28)
AUTOFD
14
AUTOFD
14
AUTOFD
17
Capacitor−Filtered (1, 2, 8, 10, 12, 15, 27, or 28)
FAULT
15
FAULT
32
FAULT
4
Capacitor−Filtered (1, 2, 8, 10, 12, 15, 27, or 28)
INIT
16
INIT
31
INIT
14
Capacitor−Filtered (1, 2, 8, 10, 12, 15, 27, or 28)
Selectin
17
Selectin
36
Selectin
16
Ground
18
Ground
19
Ground
19
Ground
19
Ground
20
Ground
20
Ground
20
Ground
21
Ground
21
Ground
21
Ground
22
Ground
22
Ground
22
Ground
23
Ground
23
Ground
23
Ground
24
Ground
24
Ground
24
Ground
25
Ground
25
Ground
25
Ground
26
Ground
26
Ground
27
Ground
27
Ground
28
Ground
28
Ground
29
Ground
29
Ground
30
Ground
30
Not Defined
33
Ground
31
Not Defined
34
Ground
32
Not Defined
35
Ground
33
Not Defined
15
Ground
34
Logic Ground
16
Ground
35
Chassis GND
17
Not Required
36
Peripheral
Logic
18
Host Logic
High
18
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QSOP28 NB
CASE 492AA−01
ISSUE O
DATE 27 MAR 2008
SCALE 2:1
M
D
28
A
B
15
H
0.25
M
B
M
h x 45 _
E
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSIONS OR FLASH. END FLASH SHALL NOT
EXCEED 0.25 PER SIDE.
DETAIL A
14
28X
e
0.25
b
M
T A
S
B
S
A
28X
0.10 C
A1
C
L
SEATING
PLANE
DIM
A
A1
b
C
D
E
e
H
h
L
M
MILLIMETERS
MAX
MIN
1.35
1.75
0.10
0.25
0.20
0.30
0.19
0.25
9.80
10.00
3.80
4.00
0.635 BSC
5.79
6.20
0.22
0.50
0.40
1.27
0_
8_
C
DETAIL A
SOLDERING FOOTPRINT
6.40
28X
1.12
1
28
28X
0.42
0.64
PITCH
14
15
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98AON26685D
QSOP28 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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