PACVGA105
VGA Port Companion Circuit
Product Description
The PACVGA105 incorporates 7 channels of ESD protection for
signal lines commonly found in a VGA port for PCs. ESD protection is
implemented with current steering diodes designed to safely handle
the high peak surge currents associated with the IEC−1000−4−2
Level−4 ESD Protection Standard (8 kV contact discharge). When
the channels are subjected to an electrostatic discharge, the ESD
current pulse is diverted via the protection diodes into the positive
supply rails or ground where they may be safely dissipated.
The upper ESD diodes for the R, G and B channels are connected to
a separate supply rail (VRGB) to facilitate interfacing to graphics
controller ICs with low voltage supplies. The remaining channels are
connected to the main 5 V rail (VCC). The lower diodes for the R, G
and B channels are also connected to a dedicated ground pin (GNDA)
to minimize crosstalk due to common ground impedance.
Two non−inverting buffers are also included in this IC for buffering
the HSYNC and VSYNC signals from the graphics controller IC.
These buffers will accept TTL input levels and convert them to CMOS
output levels that swing between GND and VCC. These drivers have
a nominal 60 W output impedance to match the characteristic
impedance of the HSYNC and VSYNC lines of the video cables
typically used. The inputs of these drivers also have high impedance
pull−ups (50 kW nom.) pulling up to the VAUX rail. In addition, the
DDC_CLOCK and DDC_DATA channels have 1.8 kW resistors
pulling these inputs up to the main 5 V (VCC) rail.
Features
Seven Channels of ESD Protection Designed to Meet
IEC−1000−4−2 Level−4 ESD Requirements (8 kV Contact
Discharge)
Very Low Loading Capacitance from ESD Protection Diodes at
Less than 5 pF Typical
TTL to CMOS Level−Translating Buffers for the HSYNC and
VSYNC Lines
Three Independent Supply Pins (VCC, VRGB and VAUX) to
Facilitate Operation with Sub−Micron Graphics Controller ICs
High impedance Pull−Ups (50 kW Nominal to VAUX) for HSYNC
and VSYNC Inputs
Pull−Up Resistors (1.8 kW Nominal to VCC) for DDC_CLK and
DDC_DATA Lines
Compact 16−Pin QSOP Package
These Devices are Pb−Free and are RoHS Compliant
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QSOP16
QR SUFFIX
CASE 492
MARKING DIAGRAM
PACVGA
105QR
YYWWG
PACVGA105QR = Specific Device Code
YY
= Year
WW
= Work Week
G
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
PACVGA105QR
QSOP16
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Applications
ESD Protection and Termination Resistors for VGA (Video) Port
Interfaces
Desktop PCs
Notebook Computers
LCD Monitors
Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 3
1
Publication Order Number:
PACVGA105/D
PACVGA105
SIMPLIFIED ELECTRICAL SCHEMATIC
VCC
VAUX
VRGB
1.8 kW
1.8 kW
50 kW
DDC_CLK
R
G
B
VSYNC_OUT
GNDD
DDC_DATA
HSYNC
VSYNC
GNDA
50 kW
HSYNC_OUT
PACKAGE / PINOUT DIAGRAMS
Top View
HSYNC_OUT
1
16
VCC
HSYNC
2
15
VSYNC_OUT
GNDD
3
14
VSYNC
VRGB
4
13
VAUX
B
5
12
DDC_CLK
G
6
11
GNDD
R
7
10
DDC_DATA
GNDA
8
9
VCC
16−Pin QSOP
Table 1. PIN DESCRIPTIONS
Lead(s)
Name
Description
1
HSYNC_OUT
2
HSYNC
Horizontal sync signal buffer input. Connects to the VGA Controller side of the horizontal sync line.
3, 11
GNDD
Digital ground reference supply pin.
4
VRGB
VRGB supply pin. This is an isolated supply pin for the R, G and B ESD protection circuits.
5
B
Blue signal video protection channel. This pin is typically tied to the B video line between the VGA
controller device and the video connector.
6
G
Green signal video protection channel. This pin is typically tied to the G video line between the VGA
controller device and the video connector.
7
R
Red signal video protection channel. This pin is typically tied to the R video line between the VGA
controller device and the video connector.
8
GNDA
9, 16
VCC
10
DDC_DATA
DDC data pin.
12
DDC_CLK
DDC clock pin.
13
VAUX
14
VSYNC
15
VSYNC_OUT
Horizontal sync signal buffer output. Connects to the video connector side of the horizontal sync line.
Analog ground reference supply pin.
VCC supply pin. This is the main supply input for the DDC_CLK and DDC_DATA pullup resistors and
ESD protection circuits. It is also connected to the sync buffers and to the ESD protection diodes
present on the HSYNC_OUT and VSYNC_OUT lines.
VAUX supply pin. This is the supply input for the 50 kW pullups connected to the HSYNC and VSYNC
buffer inputs.
Vertical sync signal buffer input. Connects to the VGA Controller side of the vertical sync line.
Vertical sync signal buffer output. Connects to the video connector side of the vertical sync line.
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2
PACVGA105
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
VCC, VRGB, VAUX Supply Voltage Inputs
Diode Forward Current (One Diode Conducting at a Time)
DC Voltage at Inputs
R, G, B
HSYNC, VSYNC
DDC_CLK, DDC_DATA
Rating
Units
[GND − 0.5] to +6.0
V
20
mA
[GND − 0.5] to [VRGB + 0.5]
[GND − 0.5] to [VAUX + 0.5]
[GND − 0.5] to [VCC + 0.5]
Operating Temperature Range
Storage Temperature Range
Package Power Rating
V
0 to +70
C
−40 to +150
C
750
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Units
VCC
Main Supply Voltage
4.5
5.5
V
VRGB
RGB Supply Voltage
1.7
3.7
V
VAUX
Auxiliary Supply Voltage
2.9
3.7
V
VIH
Logic High Input Voltage (Note 1)
2.0
VIL
Logic Low Input Voltage (Note 1)
VI
Input Voltage
RGB
HSYNC, VSYNC
DDC_CLK, DDC_DATA
V
0.8
0
0
0
VRGB
VAUX
VCC
V
V
IOH
High Level Output Current (Note 1)
−8
mA
IOL
Low Level Output Current (Note 1)
8
mA
TA
Free−Air Operating Temperature
+70
C
0
1. These parameters apply only to the HSYNC and VSYNC signals.
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3
PACVGA105
SPECIFICATIONS (Cont’d)
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
VF
Parameter
Conditions
Diode Forward Voltage
IF = 10 mA
VOH
Logic High Output Voltage
IOH = −4 mA, VCC = 4.5 V
VOL
Logic Low Output Voltage
IOL = 4 mA, VCC = 4.5 V
Input Current
R, G and B Pins
HSYNC, VSYNC Pins
HSYNC, VSYNC Pins
VRGB = 3.63 V, VIN = VRGB or GND
VAUX = 3.63 V, VIN = VAUX
VAUX = 3.63 V, VIN = GND
IIN
ICC
VCC Supply Current
VCC = 5.5 V, VAUX = VRGB = 2.97 V,
All Inputs and Outputs Floating
IRGB
VRGB Supply Current
R, G and B Pins at VCC or GND,
All Inputs and Outputs Floating
CIN
Input Capacitance
R, G and B pins
HSYNC, VSYNC pins
DDC_DATA, DDC_CLK pins
Note 2 Applies for All Cases
RPU
Pull−up Resistance
DDC_DATA, DDC_CLK pins
Min
Typ
Max
Units
1.0
V
4.0
V
0.4
−30.0
mA
−72.5
1
1
−95.0
35
100
mA
10
mA
pF
5
10
5
1.62
V
1.80
1.98
kW
VESD
ESD Withstand Voltage
VCC = 5 V, VRGB = 3.3 V, VAUX = 3.3 V
(Note 3)
kV
tPLH
SYNC Buffer L H
Propagation Delay
CL = 50 pF, VCC = 5.0 V, RL = 500 W
(Note 4)
7.0
15.0
ns
tPHL
SYNC Buffer H L
Propagation Delay
CL = 50 pF, VCC = 5.0 V, RL = 500 W
(Note 4)
7.0
15.0
ns
tR, tF
SYNC Buffer Output Rise & Fall Times
CL = 50 pF, VCC = 5.0 V, RL = 500 W
(Note 4)
7.0
8
ns
1. All parameters specified over standard operating conditions unless otherwise noted.
2. Measured at 1 MHz. R/G/B inputs biased at 1.65 V with VRGB = 3.3 V. DDC_CLK and DDC_DATA biased at 2.5 V with VCC = 5 V. HSYNC
and VSYNC inputs biased at VAUX or GND with VAUX = 3.3 V and VCC = 5 V.
3. Per the IEC−61000−4−2 International ESD Standard, Level 4 contact discharge method. VRGB and VCC must be bypassed to GND via a low
impedance ground plane with a 0.2 mF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the
applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: R, G, B, HSYNC_OUT,
VSYNC_OUT, DDC_CLK and DDC_DATA. The HSYNC and VSYNC inputs are ESD protected to the industry standard 2 kV per the Human
Body Model (MIL−STD−883, Method 3015).
4. Applicable to the SYNC buffers only. Input signals swing between 0 V and 3.0 V, with rise and fall times 5 ns. Guaranteed by correlation
to buffer output drive currents.
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4
PACVGA105
APPLICATION INFORMATION
To Video
DAC VDD
5V
0.2 mF
4
0.2 mF
9, 16
VRGB
14
Video Controller
V−Sync
10
DDC_Data
12
DDC_Clk
Blue
VAUX
GNDA
HSYNC
VSYNC
GNDD
8
3, 11
DDC_DATA
DDC_CLK
Red
Green
13
VCC
Digital
GND
Analog
GND
PACVGA105
VSYNC_OUT
1
15
7
6
5
R
G
B
SF**
ÎÎÎ
Î
ÎÎ
ÎÎÎ
SF**
VF**
VF**
VF**
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
HSYNC_OUT
Video Connector
2
H−Sync
3.3 V
H−Sync
V−Sync
DDC_Data
DDC_Clk
Red
Green
Blue
VF** − VIDEO EMI Filter
SF** − SYNC EMI Filter
Figure 1. Typical Connection Diagram
GNDA, the negative voltage rail for the R, G and B diodes is not connected internally to GNDD. GNDA should ideally be
connected to the ground of the video DAC IC. This will prevent any ground bounce caused by digital signals from injecting
noise onto the R, G and B signals. Analog GND and digital GND are typically connected on the printed circuit board.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QSOP16
CASE 492−01
ISSUE A
DATE 23 MAR 2011
2X
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT EX
CEED 0.005 PER SIDE. DIMENSION E1 DOES NOT
INCLUDE INTERLEAD FLASH OR PROTRUSION. IN
TERLEAD FLASH OR PROTRUSION SHALL NOT EX
CEED 0.005 PER SIDE. D AND E1 ARE DETERMINED
AT DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
0.20 C D
D
16
L2
D
A
9
GAUGE
PLANE
SEATING
PLANE
E
E1
C
L
C
DETAIL A
2X
2X 10 TIPS
0.20 C D
1
8
16X
e
B
b
0.25
A2
0.10 C
0.10 C
A1
16X
C
0.25 C D
M
C A-B D
h x 45 _
A
SEATING
PLANE
M
1.12
9
XXXXXXX
XXXXXXX
YYWWG
6.40
1
8
0.635
PITCH
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
1.24
---0.20
0.30
0.19
0.25
4.89 BSC
6.00 BSC
3.90 BSC
0.635 BSC
0.22
0.50
0.40
1.27
0.25 BSC
0_
8_
16X
0.42
16
DETAIL A
INCHES
MIN
MAX
0.053
0.069
0.004
0.010
0.049
---0.008
0.012
0.007
0.010
0.193 BSC
0.237 BSC
0.154 BSC
0.025 BSC
0.009
0.020
0.016
0.050
0.010 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
16X
H
DIM
A
A1
A2
b
c
D
E
E1
e
h
L
L2
M
XXXXX
YY
WW
G
= Specific Device Code
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
DIMENSIONS: MILLIMETERS
98AON04472D
QSOP16
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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