DATA SHEET
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Dual Bidirectional I2C-bus
and SMBus Voltage-Level
Translator
MARKING
DIAGRAMS
8
AAF
YWWA
G
TSSOP−8
DT SUFFIX
CASE 948AL
PCA9306
The PCA9306 is a dual bidirectional I2C−bus and SMBus
voltage−level translator with an enable (EN) input.
1
Features
• 2−bit Bidirectional Translator for SDA and SCL Lines in
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Mixed−Mode I2C−Bus Applications
Standard−Mode, Fast−Mode, and Fast−Mode Plus I2C−Bus and
SMBus Compatible
Less Than 1.5 ns Maximum Propagation Delay to Accommodate
Standard−Mode and Fast−Mode I2C−Bus Devices and Multiple
Masters
Allows Voltage Level Translation Between:
♦ 1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2)
♦ 1.2 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2)
♦ 1.8 V Vref(1) and 3.3 V or 5 V Vbias(ref)(2)
♦ 2.5 V Vref(1) and 5 V Vbias(ref)(2)
♦ 3.3 V Vref(1) and 5 V Vbias(ref)(2)
Provides Bidirectional Voltage Translation With No Direction Pin
Low 3.5 W ON−State Connection Between Input and Output Ports
Provides Less Signal Distortion
Open−Drain I2C−Bus I/O Ports (SCL1, SDA1, SCL2 and SDA2)
5 V Tolerant I2C−Bus I/O Ports to Support Mixed−Mode Signal
Operation
High−Impedance SCL1, SDA1, SCL2 and SDA2 Pins for
EN = LOW
Lock−Up Free Operation
Flow Through Pinout for Ease of Printed−Circuit Board Trace
Routing
Packages Offered:
♦ TSSOP−8, US8, UQFN8, UDFN8
ESD Performance: 4000 V Human Body Model,
400 V Machine Model
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2014
March, 2022 − Rev. 8
1
US8
US SUFFIX
CASE 493
1
Commercial
UQFN8
MU SUFFIX
CASE 523AN
8
UDFN8
1.45 x 1.0
CASE 517BZ
AAF, AK, AQ, P
A
L
Y
W, WW
M
G
AK M
G
AK
ALYW
NLV Prefix
1
AQ MG
PM
1
= Specific Device Code
= Assembly Location
= Lot Code
= Year Code
= Week Code
= Date Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Publication Order Number:
PCA9306/D
PCA9306
Function Description
bus. The PCA9306 has a standard open−collector
configuration of the I2C−bus. The size of these pull−up
resistors depends on the system, but each side of the
translator must have a pull−up resistor. The device is
designed to work with Standard−mode, Fast−mode and Fast
mode Plus I2C−bus devices in addition to SMBus devices.
The maximum frequency is dependent on the RC time
constant, but generally supports > 2 MHz.
When the SDA1 or SDA2 port is LOW, the clamp is in the
ON−state and a low resistance connection exists between the
SDA1 and SDA2 ports. Assuming the higher voltage is on
the SDA2 port, when the SDA2 port is HIGH, the voltage on
the SDA1 port is limited to the voltage set by VREF1. When
the SDA1 port is HIGH, the SDA2 port is pulled to the drain
pull−up supply voltage (Vpu(D)) by the pull−up resistors.
This functionality allows a seamless translation between
higher and lower voltages selected by the user without the
need for directional control. The SCL1/SCL2 channel also
functions as the SDA1/SDA2 channel.
All channels have the same electrical characteristics and
there is minimal deviation from one output to another in
voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication
of the switch is symmetrical. The translator provides
excellent ESD protection to lower voltage devices, and at the
same time protects less ESD−resistant devices.
The PCA9306 is a dual bidirectional I2C−bus and SMBus
voltage−level translator with an enable (EN) input, and is
operational from 1.0 V to 3.6 V (Vref(1)) and 1.8 V to 5.5 V
(Vbias(ref)(2)).
The PCA9306 allows bidirectional voltage translations
between 1.0 V and 5 V without the use of a direction pin. The
low ON−state resistance (Ron) of the switch allows
connections to be made with minimal propagation delay.
When EN is HIGH, the translator switch is on, and the SCL1
and SDA1 I/O are connected to the SCL2 and SDA2 I/O,
respectively, allowing bidirectional data flow between
ports. When EN is LOW, the translator switch is off, and a
high−impedance state exists between ports.
The PCA9306 is not a bus buffer that provides both level
translation and physical capacitance isolation to either side
of the bus when both sides are connected. The PCA9306
only isolates both sides when the device is disabled and
provides voltage level translation when active.
The PCA9306 can be used to run two buses, one at
400 kHz operating frequency and the other at 100 kHz
operating frequency. If the two buses are operating at
different frequencies, the 100 kHz bus must be isolated
when the 400 kHz operation of the other bus is required. If
the master is running at 400 kHz, the maximum system
operating frequency may be less than 400 kHz because of
the delays added by the translator.
As with the standard I2C−bus system, pull−up resistors are
required to provide the logic HIGH levels on the translator’s
FUNCTIONAL DIAGRAM
Figure 1. Logic Diagram
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2
PCA9306
PIN ASSIGNMENTS
Figure 2. TSSOP−8 / US8 Pinouts
Figure 3. UQFN8 Pinout (Top Thru View)
Figure 4. UDFN8 Pinout (Top Thru View)
Table 1. PIN DESCRIPTION
Pin
GND
VREF1
Description
Ground
Low−voltage side reference supply voltage for SCL1 and SDA1
SCL1
Serial clock, low−voltage side; connect to VREF1 through a pull−up resistor
SDA1
Serial data, low−voltage side; connect to VREF1 through a pull−up resistor
SDA2
Serial data, high−voltage side; connect to VREF2 through a pull−up resistor
SCL2
Serial clock, high−voltage side; connect to VREF2 through a pull−up resistor
VREF2
EN
High−voltage side reference supply voltage for SCL2 and SDA2
Switch enable input; connect to VREF2 and pull−up through a high resistor
Table 2. FUNCTION TABLE
Input EN (Note 1)
Function
Low
Disconnect
High
SCL1 = SCL2; SDA1 = SDA2
1. EN is controlled by the Vbias(ref)(2) logic levels and should be at least 1 V higher than Vref(1) for best translator operation.
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3
PCA9306
Table 3. MAXIMUM RATINGS
Symbol
Value
Unit
Reference Voltage (Note 2)
−0.5 to +7.0
V
Reference Bias Voltage (Note 3)
−0.5 to +7.0
V
VIN
Input Voltage
−0.5 to +7.0
V
VI/O
Input / Output Pin Voltage
−0.5 to +7.0
V
ICH
DC Channel Current
128
mA
IIK
DC Input Diode Current VIN < GND
Vref(1)
Vbias(ref)(2)
TSTG
Parameter
Storage Temperature Range
−50
mA
−65 to +150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TL = 260
°C
TJ
Junction Temperature Under Bias
TJ = 150
°C
qJA
Thermal Resistance (Note 2)
qJA = 150
°C/W
PD
Power Dissipation in Still Air at 85°C
PD = 833
mW
MSL
FR
VESD
ILATCHUP
Moisture Sensitivity
Level 1
Flammability Rating Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
ESD Withstand Voltage Human Body Mode (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
Latchup Performance Above VCC and Below GND at 125 °C (Note 6)
> 4000
> 400
N/A
V
±100
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
3. Tested to EIA / JESD22−A114−A.
4. Tested to EIA / JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA / JESD78.
Table 4. RECOMMENDED OPERATING CONDITIONS
Symbol
Vref(1)
Vbias(ref)(2)
VI/O
VI(EN)
Isw(pass)
TA
Parameter
Min
Max
Unit
Reference Voltage (1) (Note 7)
VREF1
0
5.5
V
Reference Bias Voltage (2) (Note 7)
VREF2
0
5.5
V
Input / Output Pin Voltage SCL1, SDA1, SCL2, SDA2
0
5.5
V
Control Pin Input Voltage EN
0
5.5
V
Pass Switch Current
0
64
mA
−55
+125
°C
Operating Free−Air Temperature
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
7. V(ref)(1) ≤ Vbias(ref)(2) −1 V for best results in level shifting applications.
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4
PCA9306
Table 5. DC ELECTRICAL CHARACTERISTICS
TA = −555C to +1255C
Symbol
Parameter
Conditions
VIK
Input Clamping Voltage
II = −18 mA; VI(EN) = 0 V
IIH
High−Level Input Current
VI = 5 V; VI(EN) = 0 V
Ci(EN)
EN Pin Input Capacitance
VI = 3 V or 0 V
Ci/O(off)
OFF−State I/O Pin Capacitance
SCLn, SDAn
VO = 3 V or 0 V; VI(EN) = 0 V
Ci/O(on)
ON−State I/O Pin Capacitance
SCLn, SDAn
ON−State Resistance(2)(3) SCLn, SDAn
RON
Typ
(Note 8)
Min
Max
Unit
−1.2
V
5
mA
7.1
pF
4
6
VO = 3 V or 0 V;
VI(EN) = 3 V
9.3
12.5
VI = 0 V; IO = 64 mA
VI(EN) = 4.5 V
VI(EN) = 3 V
VI(EN) = 2.3 V
VI(EN) = 1.5 V
2.4
3.0
3.8
9.0
5.0
6.0
8.0
20
VI = 2.4 V; IO = 15 mA
VI(EN) = 4.5 V
VI(EN) = 3 V
4.8
46
7.5
80
VI = 1.7 V; IO = 15 mA
VI(EN) = 2.3 V
40
80
pF
pF
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. All typical values are at TA = 25°C.
9. Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switch.
ON−state resistance is determined by the lowest voltage of the two terminals.
10. Guaranteed by design.
Table 6. AC ELECTRICAL CHARACTERISTICS (Translating Down) − Values Guaranteed by Design
Symbol
Parameter
Test Condition
Load
Condition
TA = −555C to +1255C
Min
Max
Unit
CL = 15 pF
0
0.6
ns
CL = 30 pF
0
1.2
CL = 50 pF
0
2.0
CL = 15 pF
0
0.75
CL = 30 pF
0
1.5
CL = 50 pF
0
2.0
CL = 15 pF
0
0.6
CL = 30 pF
0
1.2
CL = 50 pF
0
2.0
CL = 15 pF
0
0.75
CL = 30 pF
0
1.5
CL = 50 pF
0
2.5
SEE FIGURE 4 LOAD SWITCH AT S2 POSITION
tPLH
tPHL
tPLH
tPHL
Low−to−High Propagation Delay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
VI(EN) = 3.3 V; VIH = 3.3 V;
VIL = 0 V; VM = 1.15 V
High−to−Low Propagation Delay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
Low−to−High Propagation Delay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
VI(EN) = 2.5 V; VIH = 2.5 V;
VIL = 0 V; VM = 0.75 V
High−to−Low Propagation Delay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
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5
ns
PCA9306
Table 7. AC ELECTRICAL CHARACTERISTICS (Translating Up) − Values Guaranteed by Design
TA =
−555C to +1255C
Test Condition
Load Condition
Min
Max
Unit
VI(EN) = 3.3 V; VIH = 2.3 V;
VIL = 0 V; VTT = 3.3 V;
VM = 1.15 V
RL = 300 W, CL = 15 pF
0
0.5
ns
RL = 300 W, CL = 30 pF
0
1.0
RL = 300 W, CL = 50 pF
0
1.75
RL = 300 W, CL = 15 pF
0
0.8
RL = 300 W, CL = 30 pF
0
1.65
RL = 300 W, CL = 50 pF
0
2.75
RL = 300 W, CL = 15 pF
0
0.5
RL = 300 W, CL = 30 pF
0
1.0
RL = 300 W, CL = 50 pF
0
1.75
RL = 300 W, CL = 15 pF
0
1.0
RL = 300 W, CL = 30 pF
0
2.0
RL = 300 W, CL = 50 pF
0
3.3
Parameter
Symbol
SEE FIGURE 4 LOAD SWITCH AT S1 POSITION
tPLH
Low−to−High Propagation Delay, from (input) SCL1 or
SDA1 to (output) SCL2 or
SDA2
tPHL
High−to−Low Propagation Delay, from (input) SCL1 or
SDA1 to (output) SCL2 or
SDA2
tPLH
Low−to−High Propagation Delay, from (input) SCL1 or
SDA1 to (output) SCL2 or
SDA2
tPHL
VI(EN) = 2.5 V; VIH = 1.5 V;
VIL = 0 V; VTT = 2.5 V;
VM = 0.75 V
High−to−Low Propagation Delay, from (input) SCL1 or
SDA1 to (output) SCL2 or
SDA2
VIH
VTT
input
VM
VM
VIL
RL
from output under test
ns
VOH
S1
S2 (open)
output
VM
VM
VOL
CL
A. Load Circuit
B. Timing Diagram
S1 = translating up; S2 = translating down.
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 W; tr ≤ 2 ns; tf ≤ 2 ns.
The outputs are measured one at a time, with one transition per measurement.
Figure 5. Load Circuit for Outputs
ORDERING INFORMATION
Package
Shipping†
PCA9306DTR2G
TSSOP−8
(Pb−Free)
4000 / Tape & Reel
PCA9306AMUTCG
UQFN8
(Pb−Free)
3000 / Tape & Reel
PCA9306FMUTAG
UDFN8
(Pb−Free)
3000 / Tape & Reel
PCA9306FMUTCG
UDFN8
(Pb−Free)
3000 / Tape & Reel
PCA9306USG
US8
(Pb−Free)
3000 / Tape & Reel
Device
NLVPCA9306AMUTCG*
NLV9306USG*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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6
PCA9306
APPLICATION INFORMATION
VPU(D) = 3.3 V
(Note 1)
200 kW
VREF(1) = 1.8 V
(Note 1)
PCA9306
VREF1
RPU
2
8 EN
RPU
RPU
VREF2
7
RPU
VCC
SCL
I2C−Bus
MASTER
SDA
SCL1
3
SDA1
4
SW
SW
GND
6
SCL2
5
SDA2
VCC
SCL
I2C−Bus
DEVICE
SDA
1
GND
GND
1. The applied voltages at Vref(1) and Vpu(D) should be such that Vbias(ref)(2) is at least 1 V higher than Vref(1) for best translator
operation.
Figure 6. Typical Application (Switch Always Enabled)
VPU(D) = 3.3 V
3.3 V Enable Signal (Note 2)
OFF ON
200 kW
VREF(1) = 1.8 V
(Note 2)
PCA9306
VREF1
RPU
VCC
SCL
2
8
7
EN
RPU
RPU
VREF2
RPU
SCL1
3
6 SCL2
SW
I2C−Bus
MASTER
SDA
SDA1
4
GND
5 SDA2
SW
1
SCL
VCC
I2C−Bus
DEVICE
SDA
GND
GND
2. In the Enabled mode, the applied enable voltage and the applied voltage at Vref(1) should be such that Vbias(ref)(2) is at least 1 V
higher than Vref(1) for best translator operation.
Figure 7. Typical Application (Switch Enable Control)
Bidirectional Translation
unidirectional or the outputs must be 3−stateable and be
controlled by some direction−control mechanism to prevent
HIGH−to−LOW contentions in either direction. If both
outputs are open−drain, no direction control is needed.
The reference supply voltage (Vref(1)) is connected to the
processor core power supply voltage. When VREF2 is
connected through a 200 kW resistor to a 3.3 V to 5.5 V
Vpu(D) power supply, and Vref(1) is set between 1.0 V and
(Vpu(D) − 1 V), the output of each SCL1 and SDA1 has a
maximum output voltage equal to VREF1, and the output of
each SCL2 and SDA2 has a maximum output voltage equal
to Vpu(D).
For the bidirectional clamping configuration (higher
voltage to lower voltage or lower voltage to higher voltage),
the EN input must be connected to VREF2 and both pins
pulled to HIGH side Vpu(D) through a pull−up resistor
(typically 200 kW). This allows VREF2 to regulate the EN
input. A filter capacitor on VREF2 is recommended. The
I2C−bus master output can be totem−pole or open−drain
(pull−up resistors may be required) and the I2C−bus device
output can be totem−pole or open−drain (pull−up resistors
are required to pull the SCL2 and SDA2 outputs to Vpu(D)).
However, if either output is totem−pole, data must be
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7
PCA9306
Table 8. APPLICATION OPERATING CONDITIONS Refer to Figure 6.
Min
Typ(1)
Max
Unit
Reference Bias Voltage (2)
Vref(1) + 0.6
2.1
5
V
VI(EN)
EN Pin Input Voltage
Vref(1) + 0.6
2.1
5
V
Vref(1)
Reference Voltage (1)
0
1.5
4.4
V
Symbol
Parameter
Vbias(ref)(2)
Isw(pass)
Iref
Tamb
Conditions
Pass Switch Current
Reference Current
Transistor
Ambient Temperature
Operating in free−air
14
mA
5
mA
−55
+125
°C
11. All typical values are at Tamb = 25 °C.
Sizing Pull−up Resistor
The following table summarizes resistor reference
voltages and currents at 15 mA, 10 mA, and 3 mA. The
resistor values shown in the +10% column or a larger value
should be used to ensure that the pass voltage of the
transistor would be 350 mV or less. The external driver must
be able to sink the total current from the resistors on both
sides of the PCA9306 device at 0.175 V, although the 15 mA
only applies to current flowing through the PCA9306
device.
The pull−up resistor value needs to limit the current
through the pass transistor when it is in the ON state to about
15 mA. This ensures a pass voltage of 260 mV to 350 mV.
If the current through the pass transistor is higher than
15 mA, the pass voltage also is higher in the ON state. To set
the current through each pass transistor at 15 mA, the
pull−up resistor value is calculated as:
R PU +
V PU(D) * 0.35 V
0.015 A
(eq. 1)
Table 9. PULLUP RESISTOR VALUES Calculated for VOL = 0.35 V; assumes output driver VOL = 0.175 V at stated current.
Pullup Resistor Value (W)
15 mA
10 mA
3 mA
Vpu(D)
Nominal
+10% (Note 12)
Nominal
+10%(1)
Nominal
+10% (Note 12)
5V
310
341
465
512
1550
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
12. +10% to compensate for VCC range and resistor tolerance.
Maximum Frequency Calculation
resistor is needed on the 3.3 V side. The capacitance and line
length of concern is on the 1.8 V side since it is driven
through the ON resistance of the PCA9306. If the line length
on the 1.8 V side is long enough there can be a reflection at
the chip/terminating end of the wire when the transition time
is shorter than the time of flight of the wire because the
PCA9306 looks like a high−impedance compared to the
wire. If the wire is not too long and the lumped capacitance
is not excessive the signal will only be slightly degraded by
the series resistance added by passing through the PCA9306.
If the lumped capacitance is large the rise time will
deteriorate, the fall time is much less affected and if the rise
time is slowed down too much the duty cycle of the clock
will be degraded and at some point the clock will no longer
be useful. So the principle design consideration is to
minimize the wire length and the capacitance on the 1.8 V
side for the clock path. A pull−up resistor on the 1.8 V side
can also be used to trade a slower fall time for a faster rise
time and can also reduce the overshoot in some cases.
The maximum frequency is totally dependent upon the
specifics of the application and the device can operate >
33 MHz. Basically, the PCA9306 behaves like a wire with
the additional characteristics of transistor device physics
and should be capable of performing at higher frequencies
if used correctly.
Here are some guidelines to follow that will help
maximize the performance of the device:
• Keep trace length to a minimum by placing the
PCA9306 close to the processor.
• The trace length should be less than half the time of
flight to reduce ringing and reflections.
• The faster the edge of the signal, the higher the chance
for ringing.
• The higher the drive strength (up to 15 mA), the higher
the frequency the device can use.
In a 3.3 V to 1.8 V direction level shift, if the 3.3 V side
is being driven by a totem pole type driver no pull−up
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
US8
CASE 493
ISSUE F
DATE 01 SEP 2021
SCALE 4 :1
GENERIC
MARKING DIAGRAM*
8
XX MG
G
1
XX
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON04475D
US8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2021
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN8, 1.45x1, 0.35P
CASE 517BZ−01
ISSUE O
SCALE 4:1
2X
ÉÉ
ÉÉ
ÉÉ
0.10 C
2X
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. PACKAGE DIMENSIONS EXCLUSIVE OF
BURRS AND MOLD FLASH.
A B
D
PIN ONE
REFERENCE
DATE 18 MAY 2011
E
DIM
A
A1
A3
b
D
E
e
L
L1
TOP VIEW
A3
0.05 C
A
0.05 C
A1
SIDE VIEW
C
GENERIC
MARKING DIAGRAM*
SEATING
PLANE
e/2
e
1
4
8
5
7X
XM
L
L1
8X
BOTTOM VIEW
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
1.45 BSC
1.00 BSC
0.35 BSC
0.25
0.35
0.30
0.40
b
0.10
M
C A B
0.05
M
C
NOTE 3
1
X = Specific Device Code
M = Date Code
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
RECOMMENDED
SOLDERING FOOTPRINT*
7X
0.48
8X
0.22
1.18
0.53
1
PKG
OUTLINE
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON56796E
UDFN8, 1.45X1, 0.35P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UQFN8, 1.6x1.6, 0.5P
CASE 523AN−01
ISSUE O
8
1
SCALE 4:1
A
B
D
PIN ONE
REFERENCE
2X
0.10 C
ÉÉ
ÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
EXPOSED Cu
E
A1
DATE 26 NOV 2008
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
MOLD CMPD
A3
DETAIL B
DIM
A
A1
A3
b
D
E
e
L
L1
L3
OPTIONAL
CONSTRUCTION
2X
0.10 C
TOP VIEW
L1
(A3)
DETAIL B
L3
A
0.05 C
b
0.05 C
SIDE VIEW
(0.10)
C
A1
SEATING
PLANE
(0.15)
DETAIL A
OPTIONAL
CONSTRUCTION
GENERIC
MARKING DIAGRAM*
1
8X
8X
L3
L
XX MG
e
5
3
1
XX = Specific Device Code
M = Date Code
G
= Pb−Free Package
7
8
DETAIL A
MILLIMETERS
MIN
MAX
0.45
0.60
0.00
0.05
0.13 REF
0.15
0.25
1.60 BSC
1.60 BSC
0.50 BSC
0.35
0.45
−−−
0.15
0.25
0.35
8X
b
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.10 C A B
BOTTOM VIEW
0.05 C
NOTE 3
SOLDERING FOOTPRINT*
1.70
0.50
PITCH
1
0.35
7X
0.25
1.70
8X
0.53
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON36348E
8 PIN UQFN, 1.6X1.6, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP8, 4.4x3.0, 0.65P
CASE 948AL
ISSUE A
DATE 20 MAY 2022
q
q
GENERIC
MARKING DIAGRAM*
XXX
YWW
AG
XXX
Y
WW
A
G
= Specific Device Code
= Year
= Work Week
= Assembly Location
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34428E
TSSOP8, 4.4X3.0, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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