PCS3P8504A General Purpose Peak EMI Reduction IC
Functional Description
PCS3P8504A is a versatile, 3.3 V Timing-Safe Peak EMI reduction IC. PCS3P8504A accepts an input clock either from a fundamental Crystal or from an external reference (AC or DC coupled to XIN/CLKIN) and locks on to it delivering a 1x modulated clock output. PCS3P8504A has a SSON pin for enabling and disabling Spread Spectrum function. PCS3P8504A has an SSEXTR pin to select different deviations depending upon the value of an external resistor connected between SSEXTR and GND. Modulation Rate (MR) control selects one of the two different Modulation Rates. PCS3P8504A operates from a 3.3 V supply, and is available in an 8-pin, WDFN(2 mm x 2 mm) package.
General Features
http://onsemi.com MARKING DIAGRAMS
1 WDFN8 CASE 511AQ 1
DAMG G
DA = Specific Device Code M = Date Code G = Pb--Free Device
1x, LVCMOS Peak EMI Reduction Input frequency:
15 MHz - 50 MHz Output frequency: 15 MHz - 50 MHz Analog Deviation Selection ModRate selection option Spread Spectrum Enable/Disable Supply Voltage: 3.3 V ± 0.3 V 8-pin, WDFN 2 mm x 2 mm (TDFN) Package These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant
PIN CONFIGURATION
XIN/CLKIN 1 XOUT 2 SSON 3 GND 4 8 7 6 5 VDD SSEXTR MR ModOUT
PCS3P8504A
Application
PCS3P8504A is targeted for consumer electronics application like
DPF, MFP.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
Semiconductor Components Industries, LLC, 2010
July, 2010 - Rev. 1 -
1
Publication Order Number: PCS3P8504A/D
PCS3P8504A
SSON MR VDD
XIN/CLKIN XOUT Crystal Oscillator ModOUT PLL
GND
SSEXTR
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin# 1 2 3 4 5 6 7 8 Pin Name XIN / CLKIN XOUT SSON GND ModOUT MR SSEXTR VDD Type I O I P O I I P Description Crystal connection or External reference clock input. Crystal connection. If using an external reference, this pin should be left open. Spread Spectrum ON/OFF. Spread Spectrum function enabled when HIGH, disabled when LOW. Has an internal pull--up resistor. Ground Modulated clock output Modulation Rate Select. When LOW selects Low Modulation Rate. Selects High Modulation Rate when pulled HIGH. Has an internal pull--up resistor. Analog Deviation Selection through external resistor to GND. 3.3 V supply Voltage.
Table 2. OPERATING CONDITIONS
Symbol VDD TA CL CIN Supply Voltage Operating Temperature Load Capacitance Input Capacitance Parameter Min 3 0 Max 3.6 70 10 7 Unit V C pF pF
Table 3. ABSOLUTE MAXIMUM RATING
Symbol VDD, VIN TSTG Ts Parameter Voltage on any input pin with respect to Ground Storage temperature Max. Soldering Temperature (10 sec) Rating --0.5 to +4.6 --65 to +125 260 Unit V C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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PCS3P8504A
Table 3. ABSOLUTE MAXIMUM RATING
Symbol TJ TDV Junction Temperature Static Discharge Voltage (As per JEDEC STD22-- A114--B) Parameter Rating 150 2 Unit C kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 4. DC ELECTRICAL CHARACTERISTICS
Symbol VDD VIL VIH IIL IIH VOL VOH ICC IDD Zo Parameter Supply Voltage Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Static Supply Current Dynamic Supply Current Output Impedance VIN = 0 V VIN = VDD IOL = 8 mA IOH = --8 mA XIN / CLKIN pulled low Unloaded Output 30 2.4 50 20 2.0 25 25 0.4 Test Conditions Min 3.0 Typ 3.3 Max 3.6 0.8 Unit V V V mA mA V V mA mA Ω
Table 5. SWITCHING CHARACTERISTICS
Parameter Input Frequency* / ModOUT Duty Cycle (Notes 1 and 2) Output Rise Time (Notes 1 and 2) Output Fall Time (Notes 1 and 2) Cycle--to--Cycle Jitter (Note 2) PLL Lock Time (Note 2) Measured at VDD / 2 Measured between 20% to 80% Measured between 80% to 20% Unloaded output with SSEXTR OPEN @ 27 MHz Stable power supply, valid clock presented on XIN / CLKIN ±150 Test Conditions Min 15 45 50 Typ Max 50 55 1.8 1.6 ±250 3 Unit MHz % ns ns ps ms
*Functionality with Crystal is guaranteed by design and characterization. Not 100% tested in production. 1. All parameters are specified with10 pF loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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PCS3P8504A
TYPICAL CRYSTAL SPECIFICATIONS FUNDAMENTAL AT CUT PARALLEL RESONANT CRYSTAL
Nominal frequency Frequency tolerance Operating temperature range Storage temperature Load capacitance (CP) Shunt capacitance ESR NOTE: 27 MHz ±50 ppm or better at 25C --25C to +85C --40C to +85C 18 pF 7 pF maximum 25 Ω CL is the Load Capacitance and Rx is used to prevent oscillations at overtone frequency of the Fundamental frequency.
PCS3P8504A R
XIN/CLKIN Crystal
XOUT Rx
CL
CL
CL = 2 * (CP – CS), Where CP = Load capacitance of crystal from crystal vendor datasheet CS = Stray capacitance due to CIN, PCB, Trace etc.
Figure 2. Typical Crystal Interface Circuit
SWITCHING WAVEFORMS
t1 t2 VDD/2 OUTPUT VDD/2
VDD/2
Figure 3. Duty Cycle Timing
80% 20% OUTPUT t3
80% 20%
t4
Figure 4. Output Rise/Fall Time
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PCS3P8504A
Noise Reduction Filter R CL is the load capacitance for proper XTAL operation VDD
PCS3P8504A
1 XIN/CLKIN VDD 8
C
CL 2 XOUT SSEXTR External Deviation Control 7 VDD 3 SSON SSON Control MR 6 MR Control 4 GND ModOUT 5 R1 Analog Deviation Control SSEXTR can be Pulled HIGH to turn OFF Deviation
CL
VDD
NOTE:
SSON (Pin#3) MR (Pin#6): Connect to VDD or GND Refer to Pin Description table for Functionality details
Figure 5. Application Schematic
2.5 2.0 DEVIATION (±%)
MR = 0
2.5 2.0 DEVIATION (±%) 1.5 1.0 0.5 0.0
MR = 1
1.5 1.0 0.5 0.0
0
50
100
150
200
250
300
0
50 100 150 200 250 300 350 400 450 500 550 600 650 RESISTANCE (kΩ)
RESISTANCE (kΩ)
Figure 6. Deviation vs SSEXTR Resistance Chart at 27 MHz
NOTE: Device to Device variation of Deviation is ±10%
Figure 7. Deviation vs SSEXTR Resistance Chart at 27 MHz
ORDERING INFORMATION
Part Number PCS3P8504AG--08CR Top Marking DA Temperature 0C to +70C Package Type 8--Pin (2 mm x 2 mm) WDFN(TDFN) (Pb--Free) Shipping† Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb--Free.
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PCS3P8504A
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P CASE 511AQ--01 ISSUE A
D A B L1
PIN ONE REFERENCE 2X
L
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. DIM A A1 A3 b D E e L L1 MILLIMETERS MIN MAX 0.80 0.70 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 2.00 BSC 0.50 BSC 0.50 0.60 -----0.15
E
DETAIL A
OPTIONAL CONSTRUCTIONS
0.10 C
2X
0.10 C
TOP VIEW
DETAIL B
EXPOSED Cu
MOLD CMPD
0.05 C
8X
A3 A DETAIL B
OPTIONAL CONSTRUCTION SEATING PLANE
0.05 C
A1 SIDE VIEW
DETAIL A 1 4 8X
C
RECOMMENDED SOLDERING FOOTPRINT*
0.78
7X
L
PACKAGE OUTLINE
2.30 0.88
8 5
e/2 e BOTTOM VIEW
8X
b 0.10 C A 0.05 C
B
NOTE 3
0.35
8X
1
0.50 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Timing--Safe is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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PCS3P8504A/D