RFD14N05, RFD14N05SM, RFP14N05
Data Sheet
January 2002
14A, 50V, 0.100 Ohm, N-Channel Power
MOSFETs
Features
• 14A, 50V
These are N-channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. These transistors can be operated
directly from integrated circuits.
Formerly developmental type TA09770.
Ordering Information
PART NUMBER
PACKAGE
• rDS(ON) = 0.100Ω
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
BRAND
D
RFD14N05
TO-251AA
F14N05
RFD14N05SM
TO-252AA
F14N05
RFP14N05
TO-220AB
RFP14N05
G
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-252AA variant in the tape and reel, i.e., RFD14N05SM9A.
S
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
GATE
DRAIN (FLANGE)
SOURCE
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
©2002 Fairchild Semiconductor Corporation
RFD14N05, RFD14N05SM, RFP14N05 Rev. B
RFD14N05, RFD14N05SM, RFP14N05
TC = 25oC, Unless Otherwise Specified
Absolute Maximum Ratings
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
RFD14N05, RFD14N05SM,
RFP14N05
50
50
± 20
14
Refer to Peak Current Curve
Refer to UIS Curve
48
0.32
-55 to 175
UNITS
V
V
V
A
W
W/oC
oC
oC
oC
300
260
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
PARAMETER
BVDSS
ID = 250µA, VGS = 0V (Figure 9)
50
-
-
V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA
2
-
4
V
VDS = Rated BVDSS, VGS = 0V
-
-
25
µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 150oC
-
-
250
µA
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
Turn-On Time
Turn-On Delay Time
SYMBOL
IDSS
VGS = ±20V
-
-
±100
nA
rDS(ON)
ID = 14A, VGS = 10V, (Figure 11)
-
-
0.100
Ω
tON
VDD = 25V, ID ≈ 14A, VGS = 10V,
RGS = 25Ω, RL = 1.7Ω
(Figure 13)
-
-
60
ns
-
14
-
ns
tr
-
26
-
ns
td(OFF)
-
45
-
ns
tf
-
17
-
ns
-
-
100
ns
-
-
40
nC
-
-
25
nC
-
-
1.5
nC
-
570
-
pF
-
185
-
pF
-
50
-
pF
IGSS
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
TEST CONDITIONS
tOFF
Total Gate Charge
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 5V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to Ambient
RθJA
RθJA
VDD = 40V, ID = 14A,
RL = 2.86Ω
Ig(REF) = 0.4mA
(Figure 13)
VDS = 25V, VGS = 0V, f = 1MHz
(Figure 12)
-
-
3.125
oC/W
TO-251 and TO-252
-
-
100
oC/W
TO-220
-
-
80
oC/W
MIN
TYP
MAX
UNITS
ISD = 14A
-
-
1.5
V
ISD = 14A, dISD/dt = 100A/µs
-
-
125
ns
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage (Note 2)
Diode Reverse Recovery Time
SYMBOL
VSD
trr
TEST CONDITIONS
NOTES:
2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
©2002 Fairchild Semiconductor Corporation
RFD14N05, RFD14N05SM, RFP14N05 Rev. B
RFD14N05, RFD14N05SM, RFP14N05
Typical Performance Curves
Unless Otherwise Specified
16
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
12
8
4
0.2
0
125
50
75
100
TC , CASE TEMPERATURE (oC)
25
0
150
0
175
25
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
50
75
100
125
TC, CASE TEMPERATURE (oC)
150
175
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
0.5
0.2
0.1
PDM
0.1
0.05
t1
t2
0.02
0.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.01
10-5
10-4
10-2
10-1
10-3
t, RECTANGULAR PULSE DURATION (s)
100
101
ID, DRAIN CURRENT (A)
100
TJ = MAX RATED
SINGLE PULSE
TC = 25oC
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
10ms
DC
1
1
100ms
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
©2002 Fairchild Semiconductor Corporation
100
IDM, PEAK CURRENT CAPABILITY (A)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 20V
100
VGS = 10V
175 – T C
I = I 25 ---------------------
150
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
101
FIGURE 5. PEAK CURRENT CAPABILITY
RFD14N05, RFD14N05SM, RFP14N05 Rev. B
RFD14N05, RFD14N05SM, RFP14N05
Typical Performance Curves
Unless Otherwise Specified (Continued)
50
35
STARTING TJ = 25oC
10
STARTING TJ = 150oC
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
1
0.01
TC = 25oC
VGS = 10V
30
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
VGS = 20V
VGS = 8V
VGS = 7V
25
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
20
VGS = 6V
15
10
VGS = 5V
5
0
0.1
1
tAV, TIME IN AVALANCHE (ms)
10
VGS = 4.5V
2
4
6
VDS, DRAIN TO SOURCE VOLTAGE (V)
0
8
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 7. SATURATION CHARACTERISTICS
35
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
30
ID = 250µA
-25oC
-55oC
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
IDS(ON), DRAIN TO SOURCE CURRENT (A)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
175oC
25
20
15
10
5
1.0
0.5
0
0
2
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
0
-80
10
2.5
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.5
1.0
0.5
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
200
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
0
40
80
120
160
200
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
2.0
0
-80
-40
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
VGS(TH), NORMALIZED GATE
1.5
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS= 10V, ID = 14A
1.5
1.0
0.5
0
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
200
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
RFD14N05, RFD14N05SM, RFP14N05 Rev. B
RFD14N05, RFD14N05SM, RFP14N05
Unless Otherwise Specified (Continued)
CISS
C, CAPACITANCE (pF)
600
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
400
COSS
300
200
CRSS
100
10
VDD = BVDSS
VDD = BVDSS
45
7.5
30
5.0
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
15
0
0
I G ( REF )
20 --------------------I G ( ACT )
0
0
2.5
RL = 3.57Ω
IG(REF) = 0.4mA
VGS = 10V
5
10
15
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS , GATE TO SOURCE VOLTAGE (V)
700
500
60
VDS , DRAIN TO SOURCE VOLTAGE (V)
Typical Performance Curves
25
t, TIME (µs)
I G ( REF )
80 --------------------I G ( ACT )
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260,
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT CURRENT GATE DRIVE
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(ON)
VDS
td(OFF)
tf
tr
VDS
90%
90%
RL
VGS
+
DUT
RGS
VGS
-
VDD
©2002 Fairchild Semiconductor Corporation
10%
90%
VGS
0
FIGURE 16. SWITCHING TIME TEST CIRCUIT
10%
0
10%
50%
50%
PULSE WIDTH
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
RFD14N05, RFD14N05SM, RFP14N05 Rev. B
RFD14N05, RFD14N05SM, RFP14N05
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
VGS = 2V
DUT
IG(REF)
VGS = 10V
VGS
-
0
Qg(TH)
IG(REF)
0
FIGURE 18. GATE CHARGE TEST CIRCUIT
©2002 Fairchild Semiconductor Corporation
FIGURE 19. GATE CHARGE WAVEFORMS
RFD14N05, RFD14N05SM, RFP14N05 Rev. B
RFD14N05, RFD14N05SM, RFP14N05
PSPICE Electrical Model
.SUBCKT RFP14N05 2 1 3 ;
rev 9/12/94
CA 12 8 8.84e-10
CB 15 14 9.34e-10
CIN 6 8 5.2e-10
DPLCAP
RSCL1
RSCL2
EBREAK 11 7 17 18 62.87
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
+
GATE
9
LGATE
20
EVTO
+ 18
RGATE
VTO
-
+
21
6
+
11
EBREAK
MOS2
17
18
DBODY
-
MOS1
CIN
8
S1A
RSOURCE
7
LSOURCE
3
SOURCE
S2A
14
13
13
8
S1B
RBREAK
15
17
18
S2B
13
RVTO
CB
CA
DBREAK
RDRAIN
16
RIN
12
S1A
S1B
S2A
S2B
6
8
8
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 2.2e-3
RGATE 9 20 5.64
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 42.3e-3
RVTO 18 19 RVTOMOD 1
+ 51
5
ESCL
51
50
ESG
1
LDRAIN 2 5 1e-9
LGATE 1 9 4.34e-9
LSOURCE 3 7 3.79e-9
DRAIN
2
LDRAIN
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
IT 8 17 1
5
10
+
EGS
-
6
8
+
EDS
-
IT
14
19
VBAT
5
8
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.82
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/50,6))}
.MODEL DBDMOD D (IS = 1.5e-13 RS = 10.9e-3 TRS1 = 2.3e-3 TRS2 = -1.75e-5 CJO = 6.84e-10 TT = 4.2e-8)
.MODEL DBKMOD D (RS = 4.15e-1 TRS1 = 3.73e-3 TRS2 = -3.21e-5)
.MODEL DPLCAPMOD D (CJO = 26.2e-11 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 3.91 KP = 12.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 7.73e-4 TC2 = 2.12e-6)
.MODEL RDSMOD RES (TC1 = 5.0e-3 TC2 = 2.53e-5)
.MODEL RSCLMOD RES (TC1 = 2.05e-3 TC2 = 1.35e-5)
.MODEL RVTOMOD RES (TC1 = -4.44e-3 TC2 = -6.45e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.29 VOFF= -3.29)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.29 VOFF= -5.29)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.25 VOFF= 2.75)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.75 VOFF= -2.25)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
©2002 Fairchild Semiconductor Corporation
RFD14N05, RFD14N05SM, RFP14N05 Rev. B
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The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
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CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
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UHC™
UltraFET
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STAR*POWER is used under license
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DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
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As used herein:
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be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4