RMPA1965
US-PCS CDMA, CDMA2000-1X and WCDMA
PowerEdge™ Power Amplifier Module
Features
General Description
■ Single positive-supply operation with low power and shutdown modes
The RMPA1965 power amplifier module (PAM) is designed for
CDMA, CDMA2000-1X, WCDMA and HSDPA personal communications system (PCS) applications. The 2 stage PAM is internally matched to 50Ω to minimize the use of external
components and features a low-power mode to reduce standby
current and DC power consumption during peak phone usage.
High power-added efficiency and excellent linearity are
achieved using our InGaP Heterojunction Bipolar Transistor
(HBT) process.
■ 40% CDMA/WCDMA efficiency at +28 dBm average output
power
■ Compact lead-free compliant low-profile package
(3.0 x 3.0 x 1.0 mm nominal)
■ Internally matched to 50Ω and DC blocked RF input/output
■ Meets CDMA2000-1XRTT/WCDMA performance requirements
■ Meets HSDPA performance requirement
Device
Functional Block Diagram
(Top View)
MMIC
8 Vcc2
Vcc1 1
RF IN 2
INPUT
MATCH
OUTPUT
MATCH
Vmode 3
DC BIAS CONTROL
7 RF OUT
6 GND
5 GND
Vref 4
(paddle ground on package bottom)
©2005 Fairchild Semiconductor Corporation
RMPA1965 Rev. H
1
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RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdge™ Power Amplifier Module
April 2005
Symbol
Parameter
Vcc1, Vcc2
Supply Voltages
Vref
Reference Voltage
Vmode
Power Control Voltage
Pin
RF Input Power
TSTG
Storage Temperature
Value
Units
5.0
V
2.6 to 3.5
V
3.5
V
+10
dBm
-55 to +150
°C
Note:
1: No permanent damage with only one parameter set at extreme limit. Other parameters set to typical values.
Electrical Characteristics1
Symbol
f
Parameter
Operating Frequency
Min
Typ
1850
Max
Units
1910
MHz
Comments
CDMA Operation
SSg
Small-Signal Gain
26
dB
Po = 0dBm
Gp
Power Gain
27
24
dB
dB
Po = +28 dBm; Vmode = 0V
Po = +16dBm; Vmode ≥ 2.0V
Po
Linear Output Power
PAEd
PAEd (digital) @ +28dBm
Itot
28
16
dBm
dBm
40
%
Vmode = 0V
Vmode ≥ 2.0V
Vmode = 0V
PAEd (digital) @ +16dBm
10
%
Vmode ≥ 2.0V
PAEd (digital) @ +16dBm
25
%
Vmode ≥ 2.0V, Vcc = 1.4V
High Power Total Current
460
mA
Po = +28dBm, Vmode = 0V
Low Power Total Current
120
mA
Po = +16dBm, Vmode ≥ 2.0V
Adjacent Channel Power Ratio
IS-95
ACPR1
±1.25MHz Offset
-50
-52
dBc
dBc
Po = +28dBm; Vmode = 0V
Po = +16dBm; Vmode ≥ 2.0V
ACPR2
±2.25MHz Offset
-60
-68
dBc
dBc
Po = +28dBm; Vmode = 0V
Po = +16dBm; Vmode ≥ 2.0V
General Characteristics
VSWR
Input Impedance
NF
Noise Figure
Rx No
Receive Band Noise Power
2.0:1
4
dB
-139
dBm/Hz
Suppression3
2fo-5fo
Harmonic
S
Spurious Outputs2, 3
Ruggedness w/ Load Mismatch3
Tc
Case Operating Temperature
-50
dBc
Po ≤ +28dBm
-60
dBc
Load VSWR ≤ 5.0:1
10:1
-30
Po ≤ +28dBm; 1930 to 1990MHz
85
No permanent damage.
°C
DC Characteristics
Iccq
Quiescent Current
45
Iref
Reference Current
5
Icc(off)
Shutdown Leakage Current
1
mA
5
Vmode ≥ 2.0V
mA
Po ≤ +28dBm
µA
No applied RF signal.
Notes:
1. All parameters met at Tc = +25°C, Vcc = +3.4V, Vref = 2.85V, f = 1880MHz and load VSWR ≤ 1.2:1, unless otherwise
noted.
2. All phase angles.
3. Guaranteed by design.
2
RMPA1965 Rev. H
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RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdge™ Power Amplifier Module
Absolute Ratings1
RMPA1965 Gain vs. Frequency
Pout = 28dBm, Vcc = 3.4V, Vref = 2.85V, Vmode = 0V
RMPA1965 PAE vs. Frequency
Pout = 28dBm, Vcc = 3.4V, Vref = 2.85V, Vmode = 0V
43
30
42
41
40
28
PAE (%)
GAIN (dB)
29
27
39
38
37
26
36
35
25
1850
1880
1850
1910
-44
-54
-46
-56
-48
-58
ACPR2 (dBc)
ACPR1 (dBc)
1910
RMPA1965 ACPR2 vs. Frequency
Pout = 28dBm, Vcc = 3.4V, Vref = 2.85V, Vmode = 0V
RMPA1965 ACPR1 vs. Frequency
Pout = 28dBm, Vcc = 3.4V, Vref = 2.85V, Vmode = 0V
-50
-60
-52
-62
-54
-64
-66
-56
1850
1880
1850
1910
1880
1910
FREQUENCY (MHz)
FREQUENCY (MHz)
3
RMPA1965 Rev. H
1880
FREQUENCY (MHz)
FREQUENCY (MHz)
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RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdge™ Power Amplifier Module
Performance Data
In addition to high-power/low-power bias modes, the efficiency of the PA module can be significantly increased at backed-off RF
power levels by dynamically varying the supply voltage (Vcc) applied to the amplifier. Since mobile handsets and power amplifiers frequently operate at 10-20 dB back-off, or more, from maximum rated linear power, battery life is highly dependent on the DC power
consumed at antenna power levels in the range of 0 to +16dBm. The reduced demand on transmitted RF power allows the PA supply
voltage to be reduced for improved efficiency, while still meeting linearity requirements for CDMA modulation with excellent margin.
High-efficiency DC-DC converters are now available to implement switched-voltage operation.
With the PA module in low-power mode (Vmode = +2.0V) at+16dBm output power and supply voltages reduced from 3.4V nominal
down to 1.2V, power-added efficiency is more than doubled from 9.5 percent to nearly 25 percent (Vcc = 1.2V) while maintaining a
typical ACPR1 of –52dBc and ACPR2 of less than –61dBc. Operation at even lower levels of Vcc supply voltage are possible with a
further restriction on the maximum RF output power.
Recommended Operating Conditions
Symbol
Parameter
Min
Max
Units
1910
MHz
3.4
4.2
V
2.7
0
2.85
3.1
0.5
V
V
1.8
0
2.0
3.0
0.5
V
V
+28
+16
dBm
dBm
+85
°C
f
Operating Frequency
Vcc1, Vcc2
Supply Voltage
3.0
Vref
Reference Voltage
(Operating)
(Shutdown)
Bias Control Voltage
(Low-Power)
(High-Power)
Vmode
Pout
Tc
Typ
1850
Linear Output Power
(High-Power)
(Low-Power)
Case Operating Temperature
-30
DC Turn-On Sequence
1) Vcc1 = Vcc2 = 3.4V (typical)
2) Vref = 2.85V (typical)
3) High-Power: Vmode = 0V (Pout > 16 dBm)
Low-Power: Vmode = 2V (Pout < 16 dBm)
4
RMPA1965 Rev. H
www.fairchildsemi.com
RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdge™ Power Amplifier Module
Efficiency Improvement Applications
1965
XYTT
Z
Materials List
Qty
Item No.
1
1
G657691-1 V1
Part Number
2
2
7
3
Ref
4
Description
Vendor
PC Board
Fairchild
#142-0701-841
SMA Connector
Johnson
#2340-5211TN
Terminals
3M
Assembly, RMPA1965
Fairchild
GRM39X7R102K50V
1000pF Capacitor (0603)
Murata
ECJ-1VB1H102K
1000pF Capacitor (0603)
Panasonic
3
5
3
5 (Alt)
2
6
C3216X5R1A335M
3.3µF Capacitor (1206)
TDK
1
7
GRM39Y5V104Z16V
0.1µF Capacitor (0603)
Murata
1
7 (Alt)
ECJ-1VB1C104K
0.1µF Capacitor (0603)
Panasonic
A/R
8
SN63
Solder Paste
Indium Corp.
A/R
9
SN96
Solder Paste
Indium Corp.
Evaluation Board Schematic
3.3 µF
1
Vcc1
2
50 ohm
TRL
3
Vmode
Vref
0.1 µF
7
SMA2
RF OUT
9
(package
base)
5
RMPA1965 Rev. H
Vcc2
50 ohm
TRL
5,6
4
1000 pF
3.3 µF
8
1965
XYTT
Z
SMA1
RF IN
1000 pF
1000 pF
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RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdge™ Power Amplifier Module
Evaluation Board Layout
I/O 1 INDICATOR
TOP VIEW
8
1
mm SQ.
3
1965
XYTT
Z
2
+.100
3.00 –.050
7
6
1
XY 965
T
Z T
5
4
FRONT VIEW
1.10mm MAX.
4X R.25mm
4
5
3
6
2
BACK SIDE SOLDER MASK
0.40mm
1
2.60mm
2
7
9
1
SEE DETAIL A
1.00mm
1.00mm
0.40mm
0.10mm
0.40mm
0.10mm
8
DETAIL A
TYP.
0.20mm
BOTTOM VIEW
Signal Descriptions
Pin No.
Symbol
Description
1
Vcc1
Supply Voltage to Input Stage
2
RF In
RF Input Signal
3
Vmode
4
Vref
Reference Voltage
5
GND
Ground
6
GND
7
RF Out
8
Vcc2
High-Power/Low-Power Mode Control
Ground
RF Output Signal
Supply Voltage to Output Stage
6
RMPA1965 Rev. H
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RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdge™ Power Amplifier Module
Package Outline
CAUTION: THIS IS AN ESD SENSITIVE DEVICE.
• If the 7-day period or the environmental conditions have been
exceeded, then the dry-bake procedure must be repeated.
Precautions to Avoid Permanent Device Damage:
Solder Materials & Temperature Profile:
Reflow soldering is the preferred method of SMT attachment.
Hand soldering is not recommended.
• Cleanliness: Observe proper handling procedures to ensure
clean devices and PCBs. Devices should remain in their
original packaging until component placement to ensure no
contamination or damage to RF, DC and ground contact
areas.
Reflow Profile
• Ramp-up: During this stage the solvents are evaporated from
the solder paste. Care should be taken to prevent rapid
oxidation (or paste slump) and solder bursts caused by violent
solvent out-gassing. A typical heating rate is 1- 2°C/sec.
• Device Cleaning: Standard board cleaning techniques should
not present device problems provided that the boards are
properly dried to remove solvents or water residues.
• Pre-heat/soak: The soak temperature stage serves two
purposes; the flux is activated and the board and devices
achieve a uniform temperature. The recommended soak
condition is: 120–150 seconds at 150°C.
• Static Sensitivity: Follow ESD precautions to protect against
ESD damage:
– A properly grounded static-dissipative surface on which to
place devices.
• Reflow Zone: If the temperature is too high, then devices may
be damaged by mechanical stress due to thermal mismatch or
there may be problems due to excessive solder oxidation.
Excessive time at temperature can enhance the formation of
inter-metallic compounds at the lead/board interface and may
lead to early mechanical failure of the joint. Reflow must occur
prior to the flux being completely driven off. The duration of
peak reflow temperature should not exceed 10 seconds.
Maximum soldering temperatures should be in the range 215–
220°C, with a maximum limit of 225°C.
– Static-dissipative floor or mat.
– A properly grounded conductive wrist strap for each person
to wear while handling devices.
• General Handling: Handle the package on the top with a
vacuum collet or along the edges with a sharp pair of bent
tweezers. Avoiding damaging the RF, DC, and ground
contacts on the package bottom. Do not apply excessive
pressure to the top of the lid.
• Cooling Zone: Steep thermal gradients may give rise to
excessive thermal shock. However, rapid cooling promotes a
finer grain structure and a more crack-resistant solder joint.
The illustration below indicates the recommended soldering
profile.
• Device Storage: Devices are supplied in heat-sealed,
moisture-barrier bags. In this condition, devices are protected
and require no special storage conditions. Once the sealed
bag has been opened, devices should be stored in a dry
nitrogen environment.
Solder Joint Characteristics:
Proper operation of this device depends on a reliable void-free
attachment of the heat sink to the PWB. The solder joint should
be 95% void-free and be a consistent thickness.
Device Usage:
Fairchild recommends the following procedures prior to
assembly.
• Dry-bake devices at 125°C for 24 hours minimum. Note: The
shipping trays cannot withstand 125°C baking temperature.
Rework Considerations:
Rework of a device attached to a board is limited to reflow of the
solder with a heat gun. The device should not be subjected to
more than 225°C and reflow solder in the molten state for more
than 5 seconds. No more than 2 rework operations should be
performed.
• Assemble the dry-baked devices within 7 days of removal
from the oven.
• During the 7-day period, the devices must be stored in an
environment of less than 60% relative humidity and a
maximum temperature of 30°C
Recommended Solder Reflow Profile
240
10 SEC
220
200
183°C
180
160
140
DEG (°C)
120
100
1°C/SEC
SOAK AT 150°C
FOR 60 SEC
80
45 SEC (MAX)
ABOVE 183°C
1°C/SEC
60
40
20
0
0
60
120
180
240
300
TIME (SEC)
7
RMPA1965 Rev. H
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RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdge™ Power Amplifier Module
Applications Information
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
FAST
ActiveArray™
FASTr™
Bottomless™ FPS™
CoolFET™
FRFET™
CROSSVOLT™ GlobalOptoisolator™
DOME™
GTO™
EcoSPARK™ HiSeC™
E2CMOS™
I2C™
EnSigna™
i-Lo™
FACT™
ImpliedDisconnect™
FACT Quiet Series™
IntelliMAX™
ISOPLANAR™
LittleFET™
MICROCOUPLER™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
Across the board. Around the world.™ OPTOLOGIC
OPTOPLANAR™
The Power Franchise
PACMAN™
Programmable Active Droop™
POP™
Power247™
PowerEdge™
PowerSaver™
PowerTrench
QFET
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
µSerDes™
SILENT SWITCHER
SMART START™
SPM™
Stealth™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic
TINYOPTO™
TruTranslation™
UHC™
UltraFET
UniFET™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
2. A critical component is any component of a life
1. Life support devices or systems are devices or
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I15
8
RMPA1965 Rev. H
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RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdge™ Power Amplifier Module
TRADEMARKS
