RMPA2059

RMPA2059 3V WCDMA PowerEdge™ Power Amplifier Module General Description Features The RMPA2059 power amplifier module (PAM) is designed for WCDMA applications. The 2 stage PAM is internally matched to 50Ω to minimize the use of external components and features a low-power mode to reduce standby current and DC power consumption during peak phone usage. High power-added efficiency and excellent linearity are achieved using our InGaP Heterojunction Bipolar Transistor (HBT) process. • Single positive-supply operation and low power and shutdown modes • 40% CDMA efficiency at +27dBm average output power • Compact LCC package- 4.0 x 4.0 x 1.5 mm with industry standard pinout • Internally matched to 50Ω and DC blocked RF input/ output • Meets WCDMA performance requirements Device Absolute Ratings1 Symbol Vcc1, Vcc2 Vref Vmode Pin TSTG Parameter Min 0 2.7 0 -55 Supply Voltages Reference Voltage Power Control Voltage RF Input Power Storage Temperature Max 5.0 5.0 3.0 +5 +150 Units V V V dBm °C Note: 1: No permanent damage with only one parameter set at extreme limit. Other parameters set to typical values. Module Block Diagram VCC1, VCC2 (1, 10) PA MODULE COLLECTOR BIAS GND (3, 6, 7, 9, 11) INTERSTAGE MATCH REF IN (2) INPUT MATCHING NETWORK INPUT STAGE MMIC INPUT STAGE BIAS VREF (5) OUTPUT STAGE OUTPUT STAGE BIAS OUTPUT MATCHING NETWORK REF OUT (8) VCC=3.4V (nom) VREF=3.0V (nom) 1920-1980 MHz 50 Ohms I/O BIAS CONTROL Vmode (4) Figure 1. RMPA2059 WCDMA Power Amplifier Module Functional Block Diagram ©2004 Fairchild Semiconductor Corporation RMPA2059 Rev. D RMPA2059 September 2004 Parameter Operating Frequency CDMA MODE Gain Maximum Linear Power Out Power-Added Efficiency Adjacent Channel Leakage Ratio ±5.0 MHz Offset ±10.0 MHz Offset General Characteristics Input VSWR Noise Figure Rx Band Noise Power Harmonic Suppression4 Spurious Output4 Case Operating Temp. DC Characteristics Quiescent Current Vref Current Power Shutdown Current3 Symbol Condition Min 1920 Typ G Gp PO PAEd PO = 0dBm PO = +27dBm PO = +27dBm 40 dB dB dBm % ACLR1 ACLR2 PO = +27dBm 3GPP 3.2 03-00 DPCCH +1DPDCH -38 -48 dBc dBc 26 27 27 VSWR NF No 2.0:1 3 -139 2fo, 3fo, 4fo 5:1 Load VSWR2 Tc Iccq Iref Max 1980 -30 -60 85 -30 High Power Mode Low Power Mode Vref = 3.0V 80 40 5 Vref = 0V 16dBm) Recommended Operating Conditions1 Parameter Supply Voltage RF Input Power WCDMA Output Power Range Reference Voltage Symbol Vcc1, Vcc2 Pin Pout Vref Min 3.1 -55 2.95 Typ 3.4 0 3.0 Max 4.5 +3 +27 3.05 Units V dBm dBm V Note: 1: RF input power for WCDMA Pout = +27dBm. ©2004 Fairchild Semiconductor Corporation RMPA2059 Rev. D Precautions to Avoid Permanent Device Damage: • Cleanliness: Observe proper handling procedures to ensure clean devices and PCBs. Devices should remain in their original packaging until component placement to ensure no contamination or damage to RF, DC & ground contact areas. • Device Cleaning: Standard board cleaning techniques should not present device problems provided that the boards are properly dried to remove solvents or water residues. • Static Sensitivity: Follow ESD precautions to protect against ESD damage: – A properly grounded static-dissipative surface on which to place devices. Solder Materials & Temperature Profile: Reflow soldering is the preferred method of SMT attachment. Hand soldering is not recommended. • Reflow Profile – Ramp-up: During this stage the solvents are evaporated from the solder paste. Care should be taken to prevent rapid oxidation (or paste slump) and solder bursts caused by violent solvent out-gassing. A typical heating rate is 1- 2°C/sec. – Pre-heat/soak: The soak temperature stage serves two purposes; the flux is activated and the board and devices achieve a uniform temperature. The recommended soak condition is: 120-150 seconds at 150°C. • General Handling: Handle the package on the top with a vacuum collet or along the edges with a sharp pair of bent tweezers. Avoiding damaging the RF, DC, & ground contacts on the package bottom. Do not apply excessive pressure to the top of the lid. – Reflow Zone: If the temperature is too high, then devices may be damaged by mechanical stress due to thermal mismatch or there may be problems due to excessive solder oxidation. Excessive time at temperature can enhance the formation of intermetallic compounds at the lead/board interface and may lead to early mechanical failure of the joint. Reflow must occur prior to the flux being completely driven off. The duration of peak reflow temperature should not exceed 10 seconds. Maximum soldering temperatures should be in the range 215-220°C, with a maximum limit of 225°C. • Device Storage: Devices are supplied in heat-sealed, moisture-barrier bags. In this condition, devices are protected and require no special storage conditions. Once the sealed bag has been opened, devices should be stored in a dry nitrogen environment. – Cooling Zone: Steep thermal gradients may give rise to excessive thermal shock. However, rapid cooling promotes a finer grain structure and a more crackresistant solder joint. The illustration below indicates the recommended soldering profile. Device Usage: Fairchild recommends the following procedures prior to assembly. Solder Joint Characteristics: Proper operation of this device depends on a reliable voidfree attachment of the heatsink to the PWB. The solder joint should be 95% void-free and be a consistent thickness. – Static-dissipative floor or mat. – A properly grounded conductive wrist strap for each person to wear while handling devices. • Dry-bake devices at 125°C for 24 hours minimum. Note: The shipping trays cannot withstand 125°C baking temperature. • Assemble the dry-baked devices within 7 days of removal from the oven. Rework Considerations: Rework of a device attached to a board is limited to reflow of the solder with a heat gun. The device should not be subjected to more than 225°C and reflow solder in the molten state for more than 5 seconds. No more than 2 rework operations should be performed. • During the 7-day period, the devices must be stored in an environment of less than 60% relative humidity and a maximum temperature of 30°C • If the 7-day period or the environmental conditions have been exceeded, then the dry-bake procedure must be repeated. ©2004 Fairchild Semiconductor Corporation RMPA2059 Rev. D RMPA2059 Application Information CAUTION: THIS IS AN ESD SENSITIVE DEVICE RMPA2059 240 10 SEC 220 200 183°C 180 160 140 DEG (°C) 120 100 1°C/SEC SOAK AT 150°C FOR 60 SEC 80 45 SEC (MAX) ABOVE 183°C 1°C/SEC 60 40 20 0 0 60 120 180 240 300 TIME (SEC) Figure 4. Recommended Solder Reflow Profile ©2004 Fairchild Semiconductor Corporation RMPA2059 Rev. D TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FAST ActiveArray™ FASTr™ Bottomless™ FPS™ CoolFET™ FRFET™ CROSSVOLT™ GlobalOptoisolator™ DOME™ GTO™ EcoSPARK™ HiSeC™ E2CMOS™ I2C™ EnSigna™ i-Lo™ FACT™ ImpliedDisconnect™ FACT Quiet Series™ ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC Across the board. Around the world.™ OPTOPLANAR™ PACMAN™ The Power Franchise POP™ Programmable Active Droop™ Power247™ PowerEdge™ PowerSaver™ PowerTrench QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ µSerDes™ SILENT SWITCHER SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic TINYOPTO™ TruTranslation™ UHC™ UltraFET VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I13