SG3525A

SG3525A Pulse Width Modulator Control Circuit The SG3525A pulse width modulator control circuit offers improved performance and lower external parts count when implemented for controlling all types of switching power supplies. The on−chip +5.1 V reference is trimmed to "1% and the error amplifier has an input common−mode voltage range that includes the reference voltage, thus eliminating the need for external divider resistors. A sync input to the oscillator enables multiple units to be slaved or a single unit to be synchronized to an external system clock. A wide range of deadtime can be programmed by a single resistor connected between the CT and Discharge pins. This device also features built−in soft−start circuitry, requiring only an external timing capacitor. A shutdown pin controls both the soft−start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft−start recycle with longer shutdown commands. The under voltage lockout inhibits the outputs and the changing of the soft−start capacitor when VCC is below nominal. The output stages are totem−pole design capable of sinking and sourcing in excess of 200 mA. The output stage of the SG3525A features NOR logic resulting in a low output for an off−state. Features http://onsemi.com MARKING DIAGRAMS 16 PDIP−16 N SUFFIX CASE 648 16 1 16 16 SOIC−16L DW SUFFIX CASE 751G 1 1 1 SG3525AN AWLYYWW SG3525A AWLYYWW • • • • • • • • • • 8.0 V to 35 V Operation 5.1 V " 1.0% Trimmed Reference 100 Hz to 400 kHz Oscillator Range Separate Oscillator Sync Pin Adjustable Deadtime Control Input Undervoltage Lockout Latching PWM to Prevent Multiple Pulses Pulse−by−Pulse Shutdown Dual Source/Sink Outputs: "400 mA Peak Pb−Free Packages are Available* A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS Inv. Input Noninv. Input Sync OSC. Output CT RT Discharge Soft−Start 1 2 3 4 5 6 7 8 (Top View) 16 Vref 15 VCC 14 Output B 13 VC 12 Ground 11 Output A 10 Shutdown 9 Compensation ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 1 January, 2005 − Rev. 5 Publication Order Number: SG3525A/D SG3525A 16 Vref 15 VCC 12 Ground OSC Output Sync RT CT Discharge Compensation INV. Input 2 Noninv. Input 8 CSoft−Start 10 Shutdown 5.0k 5.0k 4 3 6 5 7 R 9 1 − Error Amp + + − PWM − 50mA VREF S Latch S Oscillator F/F Q Q NOR Reference Regulator To Internal Circuitry Under− Voltage Lockout NOR VC 13 Output A 11 14 Output B SG3525A Output Stage Figure 1. Representative Block Diagram ORDERING INFORMATION Device SG3525AN SG3525ANG SG3525ADW SG3525ADWG SG3525ADWR2 SG3525ADWR2G Package PDIP−16 PDIP−16 (Pb−Free) SOIC−16L SOIC−16L (Pb−Free) SOIC−16L SOIC−16L (Pb−Free) Shipping† 25 Units / Rail 25 Units / Rail 47 Units / Rail 47 Units / Rail 1000 Tape & Reel 1000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 SG3525A MAXIMUM RATINGS Rating Supply Voltage Collector Supply Voltage Logic Inputs Analog Inputs Output Current, Source or Sink Reference Output Current Oscillator Charging Current Power Dissipation TA = +25°C (Note 1) TC = +25°C (Note 2) Thermal Resistance, Junction−to−Air Thermal Resistance, Junction−to−Case Operating Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 seconds) PD 1000 2000 RqJA RqJC TJ Tstg TSolder 100 60 +150 −55 to +125 +300 °C/W °C/W °C °C °C IO Iref Symbol VCC VC Value +40 +40 −0.3 to +5.5 −0.3 to VCC ±500 50 5.0 Unit Vdc Vdc V V mA mA mA mW Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Derate at 10 mW/°C for ambient temperatures above +50°C. 2. Derate at 16 mW/°C for case temperatures above +25°C. RECOMMENDED OPERATING CONDITIONS Characteristics Supply Voltage Collector Supply Voltage Output Sink/Source Current (Steady State) (Peak) Reference Load Current Oscillator Frequency Range Oscillator Timing Resistor Oscillator Timing Capacitor Deadtime Resistor Range Operating Ambient Temperature Range Symbol VCC VC IO 0 0 Iref fosc RT CT RD TA 0 0.1 2.0 0.001 0 0 Min 8.0 4.5 Max 35 35 ±100 ±400 20 400 150 0.2 500 +70 mA kHz kW mF W °C Unit Vdc Vdc mA APPLICATION INFORMATION Shutdown Options (See Block Diagram, page 2) Since both the compensation and soft−start terminals (Pins 9 and 8) have current source pull−ups, either can readily accept a pull−down signal which only has to sink a maximum of 100 mA to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions: the PWM latch is immediately set providing the fastest turn−off signal to the outputs; and a 150 mA current sink begins to discharge the external soft−start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft−start capacitor, thus, allowing, for example, a convenient implementation of pulse−by−pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn−on upon release. Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation. http://onsemi.com 3 SG3525A ELECTRICAL CHARACTERISTICS (VCC = +20 Vdc, TA = Tlow to Thigh [Note 3], unless otherwise noted.) Characteristics REFERENCE SECTION Reference Output Voltage (TJ = +25°C) Line Regulation (+8.0 V ≤ VCC ≤ +35 V) Load Regulation (0 mA ≤ IL ≤ 20 mA) Temperature Stability Total Output Variation Includes Line and Load Regulation over Temperature Short Circuit Current (Vref = 0 V, TJ = +25°C) Output Noise Voltage (10 Hz ≤ f ≤ 10 kHz, TJ = +25°C) Long Term Stability (TJ = +125°C) (Note 4) OSCILLATOR SECTION (Note 5, unless otherwise noted.) Initial Accuracy (TJ = +25°C) Frequency Stability with Voltage (+8.0 V ≤ VCC ≤ +35 V) Frequency Stability with Temperature Minimum Frequency (RT = 150 kW, CT = 0.2 mF) Maximum Frequency (RT = 2.0 kW, CT = 1.0 nF) Current Mirror (IRT = 2.0 mA) Clock Amplitude Clock Width (TJ = +25°C) Sync Threshold Sync Input Current (Sync Voltage = +3.5 V) ERROR AMPLIFIER SECTION (VCM = +5.1 V) Input Offset Voltage Input Bias Current Input Offset Current DC Open Loop Gain (RL ≥ 10 MW) Low Level Output Voltage High Level Output Voltage Common Mode Rejection Ratio (+1.5 V ≤ VCM ≤ +5.2 V) Power Supply Rejection Ratio (+8.0 V ≤ VCC ≤ +35 V) PWM COMPARATOR SECTION Minimum Duty Cycle Maximum Duty Cycle Input Threshold, Zero Duty Cycle (Note 5) Input Threshold, Maximum Duty Cycle (Note 5) Input Bias Current DCmin DCmax Vth Vth IIB − 45 0.6 − − − 49 0.9 3.3 0.05 0 − − 3.6 1.0 % % V V mA VIO IIB IIO AVOL VOL VOH CMRR PSRR − − − 60 − 3.8 60 50 2.0 1.0 − 75 0.2 5.6 75 60 10 10 1.0 − 0.5 − − − mV mA mA dB V V dB dB Dfosc DVCC Dfosc DT fmin fmax − − − − 400 1.7 3.0 0.3 1.2 − ±2.0 ±1.0 ±0.3 50 − 2.0 3.5 0.5 2.0 1.0 ±6.0 ±2.0 − − − 2.2 − 1.0 2.8 2.5 % % % Hz kHz mA V ms V mA Vref Regline Regload DVref/DT DVref ISC Vn S 5.00 − − − 4.95 − − − 5.10 10 20 20 − 80 40 20 5.20 20 50 − 5.25 100 200 50 Vdc mV mV mV Vdc mA mVrms mV/khr Symbol Min Typ Max Unit 3. Tlow = 0° Thigh = +70°C 4. Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from lot to lot. 5. Tested at fosc = 40 kHz (RT = 3.6 kW, CT = 0.01 mF, RD = 0 W). http://onsemi.com 4 SG3525A ELECTRICAL CHARACTERISTICS (continued) Characteristics SOFT−START SECTION Soft−Start Current (Vshutdown = 0 V) Soft−Start Voltage (Vshutdown = 2.0 V) Shutdown Input Current (Vshutdown = 2.5 V) OUTPUT DRIVERS (Each Output, VCC = +20 V) Output Low Level (Isink = 20 mA) (Isink = 100 mA) Output High Level (Isource = 20 mA) (Isource = 100 mA) Under Voltage Lockout (V8 and V9 = High) Collector Leakage, VC = +35 V (Note 6) Rise Time (CL = 1.0 nF, TJ = 25°C) Fall Time (CL = 1.0 nF, TJ = 25°C) Shutdown Delay (VDS = +3.0 V, CS = 0, TJ = +25°C) Supply Current (VCC = +35 V) 6. Applies to SG3525A only, due to polarity of output pulses. VOL − − VOH 18 17 VUL IC(leak) tr tf tds ICC 6.0 − − − − − 19 18 7.0 − 100 50 0.2 14 − − 8.0 200 600 300 0.5 20 V mA ns ns ms mA 0.2 1.0 0.4 2.0 V V 25 − − 50 0.4 0.4 80 0.6 1.0 mA V mA Symbol Min Typ Max Unit Vref Clock 0.1 16 Reference Regulator Flip/ Flop O s c i l l a t o r 15 0.1 VCC VC 0.1 Out A 4 3.0k PWM ADJ. Sync 3 1.0k RT 6 Deadtime 1.5k 0.009 Ramp 100W 0.1 0.001 Comp 10k 1 = VIO 2 = 1(+) 3 = 1(−) 1 2 − V/I Meter + 3 1 2 3 1 2 3 DUT 0.01 1 2 3 1 2 − E/A + 9 7 5 13 A 11 1.0k, 1.0W (2) B 14 Out B PWM 50mA 12 GND Softstart + 5.0mF Vref 2.0k Shutdown 8 5.0k 5.0k 10 Figure 2. Lab Test Fixture http://onsemi.com 5 SG3525A 200 100 RT, TIMING RESISTOR (k Ω ) 50 20 10 6 5 RT * RD = 0 W 500 R D , DEAD TIME RESISTOR (Ω ) 400 300 200 100 0 5.0 2.0 2.0 5.0 10 20 50 RD * CT 7 100 200 500 1000 2000 5000 10,000 CHARGE TIME (ms) 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 DISCHARGE TIME (ms) Figure 3. Oscillator Charge Time versus RT Figure 4. Oscillator Discharge Time versus RD 1 2 − + 9 V sat , SATURATION VOLTAGE (V) A VOL, VOLTAGE GAIN (dB) 100 80 60 40 20 0 −20 1.0 10 100 1.0 k 10 k 100 k 1.0 M RZ = 20 k CP RZ 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0.01 VCC = +20 V TJ = +25°C Source Sat, (VC−VOH) Sink Sat, (VOL) 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 IO, OUTPUT SOURCE OR SINK CURRENT (A) 10 M f, FREQUENCY (Hz) Figure 5. Error Amplifier Open Loop Frequency Response Figure 6. Output Saturation Characteristics Vref 16 Q1 Q5 Q8 7.4k 15 VCC Q3 RT CT 6 5 Q3 Q6 Q9 2.0k Q10 Ramp To PWM 25k Blanking Q14 To Output Inverting Q1 Input 1 Noninverting Input 2 200mA Q4 Q2 To PWM Comparator 100mA 5.8V 30 9 Compensation 14k Q11 3 Sync 7 Discharge Q2 12 GND 2.0k 5.0pF Q4 Q7 1.0k 400mA 23k 1.0k Q12 Q13 3.0k 250 4 OSC Output Figure 7. Oscillator Schematic Figure 8. Error Amplifier Schematic http://onsemi.com 6 SG3525A VCC Q5 Q7 Q9 Q4 Vref Q6 2.0k Q1 Q2 Q3 Q6 Omitted in SG3527A Q10 5.0k Q8 11, 14 Q11 Output 13 VC 5.0k Clock F/F 10k 10k PWM Figure 9. Output Circuit (1/2 Circuit Shown) Q1 +Vsupply To Output Filter R1 R2 13 VC SG3525A B GND 12 A 11 14 +Vsupply R1 13 VC A SG3525A 14 GND B R3 Q2 11 Q1 R2 C2 C1 T1 12 For single−ended supplies, the driver outputs are grounded. The VC terminal is switched to ground by the totem−pole source transistors on alternate oscillator cycles. In conventional push−pull bipolar designs, forward base drive is controlled by R1−R3. Rapid turn−off times for the power devices are achieved with speed−up capacitors C1 and C2. Figure 10. Single−Ended Supply Figure 11. Push−Pull Configuration +Vsupply R1 13 VC A Q1 T1 +Vsupply Q1 T1 13 11 VC A SG3525A 14 Q2 GND B 12 14 C2 R2 R1 Q2 T2 C1 11 SG3525A GND B 12 The low source impedance of the output drivers provides rapid charging of power FET input capacitance while minimizing external components. Low power transformers can be driven directly by the SG3525A. Automatic reset occurs during deadtime, when both ends of the primary winding are switched to ground. Figure 12. Driving Power FETS Figure 13. Driving Transformers in a Half−Bridge Configuration http://onsemi.com 7 SG3525A PACKAGE DIMENSIONS PDIP−16 N SUFFIX CASE 648−08 ISSUE T −A− 16 9 B 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. F S C L −T− H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 http://onsemi.com 8 SG3525A PACKAGE DIMENSIONS SOIC−16L DW SUFFIX CASE 751G−03 ISSUE C D 16 M 9 A q h X 45 _ 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_ H M B 8X 1 8 16X B TA S 0.25 M B S A E B A1 14X e SEATING PLANE T C http://onsemi.com 9 L SG3525A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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