DATA SHEET
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ESD Protection Diode Array,
5-Line
TSOP−6 FIVE SURGE
PROTECTION
350 W PEAK POWER
SMS05C, SMS12C, SMS15C,
SMS24C
This 5−line surge protection array is designed for application
requiring transient voltage protection capability. It is intended for use
in over−transient voltage and ESD sensitive equipment such as
computers, printers, automotive electronics, networking
communication and other applications. This device features a
monolithic common anode design which protects five independent
lines in a single TSOP−6 package.
PIN ASSIGNMENT
6
1
TSOP−6
CASE 318G
6
2
5
3
4
PIN 1.
2.
3.
4.
5.
6.
SCALE 2:1
Features
• Protects up to 5 Lines in a Single TSOP−6 Package
• Peak Power Dissipation − 350 W (8 20 ms Waveform)
• ESD Rating of Class 3B (Exceeding 8.0 kV) per Human Body Model
1
CATHODE
ANODE
CATHODE
CATHODE
CATHODE
CATHODE
MARKING DIAGRAM
and Class C (Exceeding 400 V) per Machine Model
• Compliance with IEC 61000−4−2 (ESD) 15 kV (Air), 8.0 kV
•
•
•
(Contact)
Flammability Rating of UL 94 V−0
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These are Pb−Free Devices
Applications
•
•
•
•
•
Hand−Held Portable Applications
Networking and Telecom
Automotive Electronics
Serial and Parallel Ports
Notebooks, Desktops, Servers
6x MG
G
x = SMS05C:J
= SMS12C:K
= SMS15C:L
= SMS24C:M
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
TSOP−6
(Pb−Free)
3000 / Tape & Reel
SMS05CT1G
SMS12CT1G
MAXIMUM RATINGS (TJ = 25°C unless otherwise specified)
SMS15CT1G
Symbol
Rating
Value
Unit
PPK 1
Peak Power Dissipation
8
20 ms Double Exponential Waveform
(Note 1)
350
W
SMS24CT1G
SZSMS24CT1G
Operating Junction Temperature Range
−40 to 150
°C
Storage Temperature Range
−55 to 150
°C
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
TJ
TSTG
TL
Lead Solder Temperature (10 s)
260
°C
ESD
Human Body Model ( HBM)
Machine Model (MM)
IEC 61000−4−2 Air (ESD)
IEC 61000−4−2 Contact (ESD)
>8000
>400
>15000
>8000
V
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Non−repetitive current pulse per Figure 3.
© Semiconductor Components Industries, LLC, 2011
November, 2021 − Rev. 9
1
Publication Order Number:
SMS05C/D
SMS05C, SMS12C, SMS15C, SMS24C
SMS05C ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
VRWM
VBR
Conditions
Min
Typ
(Note 2)
IT = 1.0 mA (Note 3)
6.2
Max
Unit
5.0
V
7.2
V
5.0
mA
Reverse Leakage Current
IR
VRWM = 5.0 V
Clamping Voltage
VC
IPP = 5.0 A (8
20 ms Waveform)
9.8
V
Clamping Voltage
VC
IPP = 24 A (8
20 ms Waveform)
14.5
V
Maximum Peak Pulse Current
IPP
8
Capacitance
CJ
VR = 0 V, f = 1.0 MHz (Line to GND)
24
A
260
400
pF
Typ
Max
Unit
12
V
15
V
20 ms Waveform
SMS12C ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
VRWM
VBR
Conditions
Min
(Note 2)
IT = 1.0 mA (Note 3)
13.3
Reverse Leakage Current
IR
VRWM = 12 V
1.0
mA
Clamping Voltage
VC
IPP = 5.0 A (8
20 ms Waveform)
0.001
19
V
Clamping Voltage
VC
IPP = 15 A (8
20 ms Waveform)
23
V
Maximum Peak Pulse Current
IPP
8
15
A
Capacitance
CJ
VR = 0 V, f = 1.0 MHz (Line to GND)
120
150
pF
Typ
Max
Unit
15
V
19
V
1.0
mA
20 ms Waveform
SMS15C ELECTRICAL CHARACTERISTICS (TJ = 25°C, unless otherwise specified) (See Note 4)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
VRWM
VBR
Conditions
Min
(Note 2)
IT = 1.0 mA (Note 3)
17
Reverse Leakage Current
IR
VRWM = 15 V
0.05
Clamping Voltage
VC
IPP = 5.0 A (8
20 ms Waveform)
24
V
Clamping Voltage
VC
IPP = 12 A (8
20 ms Waveform)
29
V
Maximum Peak Pulse Current
IPP
8
Capacitance
CJ
VR = 0 V, f = 1.0 MHz (Line to GND)
12
A
95
125
pF
Typ
Max
Unit
24
V
32
V
1.0
mA
40
V
44
V
8.0
A
75
pF
20 ms Waveform
SZ/SMS24C ELECTRICAL CHARACTERISTICS (TJ = 25°C, unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
VRWM
VBR
Conditions
Min
(Note 2)
IT = 1.0 mA (Note 3)
Reverse Leakage Current
IR
VRWM = 24 V
Clamping Voltage
VC
IPP = 5.0 A (8
Clamping Voltage
VC
IPP = 8 A (8
Maximum Peak Pulse Current
IPP
8
Capacitance
CJ
VR = 0 V, f = 1.0 MHz (Line to GND)
26.7
0.001
20 ms Waveform)
20 ms Waveform)
20 ms Waveform
60
2. Surge protection devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater
than the DC or continuous peak operating voltage level.
3. VBR is measured at pulse test current IT.
4. Parametrics are the same for the Pb−Free packages, which are suffixed with a “G’’.
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2
SMS05C, SMS12C, SMS15C, SMS24C
100
100
90
90
% OF PEAK PULSE CURRENT
PEAK PULSE DERATING IN % OF PEAK POWER
OR CURRENT @ TA = 25 ° C
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise specified)
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
150
175
PEAK VALUE IRSM @ 8 ms
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
80
70
60
HALF VALUE IRSM/2 @ 20 ms
50
40
30
tP
20
10
0
200
tr
0
20
Figure 1. Pulse Derating Curve
SZ/SMS24C
45
40
35
8 x 20 ms
PULSE WAVEFORM
SMS15C
30
SMS12C
25
20
SMS05C
15
10
5
0
0
5
10
15
80
60
Figure 2. 8 × 20 ms Pulse Waveform
20
300
JUNCTION CAPACITANCE (pF)
VC, CLAMPING VOLTAGE (V)
50
40
t, TIME (ms)
TA, AMBIENT TEMPERATURE (°C)
250
200
SMS05C
150
100
SMS12C
50
0
25
f = 1.0 MHz
SMS15C
0
IPP, PEAK PULSE CURRENT (A)
5
10
SZ/SMS24C
15
20
25
VBR, REVERSE VOLTAGE (V)
Figure 3. Clamping Voltage vs. Peak Pulse Current
Figure 4. Junction Capacitance vs. Reverse Voltage
Figure 5. ESD Pulse IEC 61000−4−2
(8.0 kV Contact)
Figure 6. SMS15CT1 ESD Response for IEC
61000−4−2 (+8.0 kV Contact)
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3
SMS05C, SMS12C, SMS15C, SMS24C
TYPICAL COMMON ANODE APPLICATIONS
A 5 surge protection junction common anode design in a
TSOP−6 package protects four separate lines using only one
package. This adds flexibility and creativity to PCB design
especially when board space is at a premium. A simplified
example of SMS05C Series Device applications is
illustrated below.
A
KEYBOARD
TERMINAL
PRINTER
ETC.
B
C
I/O
D
FUNCTIONAL
DECODER
E
GND
SMS05C SERIES DEVICE
Figure 7. Computer Interface Protection
VDD
VGG
ADDRESS BUS
RAM
ROM
DATA BUS
CPU
I/O
CLOCK
CONTROL BUS
GND
SMS05C SERIES DEVICE
Figure 8. Microprocessor Protection
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
1
SCALE 2:1
D
H
ÉÉÉ
ÉÉÉ
6
E1
1
5
2
L2
4
GAUGE
PLANE
E
3
NOTE 5
L
b
DETAIL Z
e
A
0.05
M
C
SEATING
PLANE
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
c
A1
DATE 12 JUN 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
DETAIL Z
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
2.75
3.00
1.50
1.70
0.95
1.05
0.40
0.60
0.25 BSC
10°
−
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
6. COLLECTOR 2
STYLE 3:
PIN 1. ENABLE
2. N/C
3. R BOOST
4. Vz
5. V in
6. V out
STYLE 4:
PIN 1. N/C
2. V in
3. NOT USED
4. GROUND
5. ENABLE
6. LOAD
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 6:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 7:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. N/C
5. COLLECTOR
6. EMITTER
STYLE 8:
PIN 1. Vbus
2. D(in)
3. D(in)+
4. D(out)+
5. D(out)
6. GND
STYLE 9:
PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATE
STYLE 10:
PIN 1. D(OUT)+
2. GND
3. D(OUT)−
4. D(IN)−
5. VBUS
6. D(IN)+
STYLE 11:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1/GATE 2
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
4. I/O
5. VCC
6. I/O
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
4. DRAIN
5. N/C
6. CATHODE
STYLE 16:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 17:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
XXXAYWG
G
1
6X
3.20
0.95
XXX
A
Y
W
G
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14888C
TSOP−6
IC
= Specific Device Code
=Assembly Location
= Year
= Work Week
= Pb−Free Package
XXX MG
G
1
STANDARD
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
*This information is generic. Please refer to device data
sheet for actual part marking. Pb−Free indicator, “G”
or microdot “G”, may or may not be present. Some
products may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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