STK554U362C-E

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Output stage uses IGBT / FRD technology and implements Under Voltage Protection (UVP) and Over Current Protection (OCP) with a Fault Detection output flag. Internal Boost diodes are provided for high side gate boost drive. Function  Single control power supply due to Internal bootstrap circuit for high side pre-driver circuit  All control inputs and status outputs are at low voltage levels directly compatible with microcontrollers.  A single power supply drive is enabled through the use of bootstrap circuits for upper power supplies  Built-in dead-time for shoot-thru protection  Having open emitter output for low side IGBTs ; individual shunt resistor per phase for OCP  Externally accessible embedded thermistor for substrate temperature measurement  Shutdown function ‘ITRIP’ to disable all operations of the 6 phase output stage by external input www.onsemi.com ORDERING INFORMATION See detailed ordering and shipping information on page 15 of this data sheet. Certification  UL1557 (File number : E339285) Specifications Absolute Maximum Ratings at Tc = 25C Parameter Supply voltage Collector-emitter voltage Symbol VCC VCE Remarks V+ to U-, V-, W-, surge < 500 V V+ to U, V, W or U, V, W, to U-, V-, WV+,U-,V-,W-,U,V,W terminal current Ratings Output current Io Output peak current Pre-driver voltage Iop VD1, 2, 3, 4 V+,U-,V-,W-,U,V,W terminal current, Tc = 100C V+,U-,V-,W-,U,V,W terminal current, P.W. = 1 ms VB1 to U, VB2 to V, VB3 to W, VDD to VSS *2 Input signal voltage VIN HIN1, 2, 3, LIN1, 2, 3 450 600 ±10 ±7 ±20 20 0.3 to VDD FLTEN terminal voltage VFLTEN FLTEN terminal 0.3 to VDD V Maximum power dissipation Pd IGBT per 1 channel 30 Junction temperature Tj IGBT, FRD, Pre-Driver IC 150 Storage temperature Tstg 40 to +125 Operating case temperature Tc IPM case 40 to +100 Tightening torque A screw part *3 0.9 Withstand voltage Vis 50 Hz sine wave AC 1 minute *4 2000 Reference voltage is “VSS” terminal voltage unless otherwise specified. *1 : Surge voltage developed by the switching operation due to the wiring inductance between + and U- (V-, W-) terminal. *2 : VD1 = VB1 to U, VD2 = VB2 to V, VD3 = VB3 to W, VD4 = VDD to VSS terminal voltage. *3 : Flatness of the heat-sink should be less than 50 m to +100 m. *4 : Test conditions : AC 2500 V, 1 second W *1 Unit V V A A A V V C C C Nm VRMS Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. © Semiconductor Components Industries, LLC, 2017 August 2017 - Rev. 3 1 Publication Order Number : STK554U362C-E/D STK554U362C-E Electrical Characteristics at Tc = 25C, VD1, VD2, VD3, VD4 = 15 V Parameter Symbol Conditions Test circuit Min Typ Max Unit Power output section Collector-emitter cut-off current ICE VCE = 600 V Bootstrap diode reverse current IR(BD) VR(BD) = 600 V Collector to emitter saturation voltage VCE(SAT) Diode forward voltage VF Junction to case thermal resistance Io = 10 A, Tj = 25C Io = 5 A, Tj = 100C Io = 10 A, Tj = 25C Io = 5 A, Tj = 100C θj-c(T) IGBT θj-c(D) FWD Fig.1 Fig.2 Fig.3 - - - 100 μA - - 100 μA - 1.6 2.2 1.35 - 1.6 2.1 1.3 - - - 4 - - 5 - 0.08 0.4 - 1.6 4 V V C/W Control (Pre-driver) section Pre-driver power dissipation ID High level Input voltage Vin H Low level Input voltage Vin L VD1, 2, 3 = 15 V VD4 = 15 V Fig.4 mA HIN1, HIN2, HIN3, LIN1, LIN2, LIN3 to VSS - 2.5 - - V - - - 0.8 V μA Logic 1 input leakage current IIN+ VIN = +3.3 V - - 100 143 Logic 0 input leakage current IIN- VIN = 0 V - - - 2 μA FLTEN terminal sink current IoSD - - 2 - mA FLTEN clearance delay time FLTCLR FAULT : ON / VFLTEN = 0.1 V From time fault condition clear - 1.3 1.65 2 ms VEN+ VEN rising - - - 2.5 V V FLTEN Threshold VEN- VEN falling - 0.8 - - ITRIP threshold voltage VITRIP ITRIP(16) to VSS(29) - 0.44 0.49 0.54 V ITRIP to shutdown propagation delay tITRIP - 340 550 800 ns - 250 350 - ns - 10.5 11.1 11.7 V - 10.3 10.9 11.5 V - 0.14 0.2 - V - 42.3 47 51.7 kΩ ITRIP blanking time tITRIPBL VCC and VBS supply undervoltage VCCUV+ VBSUV+ protection reset VCC and VBS supply undervoltage VCCUVVBSUVprotection set VCC and VBS supply undervoltage VCCUVH VBSUVH hysteresis Thermistor for substrate temperature Resistance between Rt Monitor TH(27) and VSS(29) Reference voltage is “VSS” terminal voltage unless otherwise specified. www.onsemi.com 2 STK554U362C-E Parameter Symbol Conditions Test circuit Min Typ Max Unit - 0.4 - - 0.65 - - 130 - μJ - 122 - μJ - 252 - μJ - 156 - μJ - 154 - μJ - 310 - μJ - - 6.9 - μJ - - 57 - ns Switching Character Switching time Turn-on switching loss t ON t OFF Eon Io = 10 A Inductive load Fig.5 + Ic = 5 A, V = 300 V, VDD = 15 V, L = 650 μH Tc = 25C μs Turn-off switching loss Eoff Total switching loss Etot Turn-on switching loss Eon Turn-off switching loss Eoff Total switching loss Etot Diode reverse recovery energy Erec Diode reverse recovery time Trr IF = 5 A, V = 400 V, VDD = 15 V, L = 650 μH, Tc = 100C Reverse bias safe operating area RBSOA Io = 20 A, VCE = 450 V - Short circuit safe operating area SCSOA VCE = 400 V, Tc = 100C - 4 - - μs Allowable offset voltage slew rate dv/dt Between U (V, W) to U- (V-, W-) - 50 - 50 V/ns Fig.5 + Ic = 5A, V = 300 V, VDD = 15 V, L = 650 μH Tc = 100C + Fig.5 Full square- - Reference voltage is “VSS” terminal voltage unless otherwise specified. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Notes 1. The pre-drive power supply low voltage protection has approximately 200 mV of hysteresis and operates as follows. Upper side ：The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will continue till the input signal will turn ‘low’. Lower side ：The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input signal voltage. 2. When assembling the IPM on the heat sink the tightening torque range is 0.6 Nm to 0.9 Nm. 3. The pre-drive low voltage protection protects the device when the pre-drive supply voltage falls due to an operating malfunction. 4. When use the over-current protection with external shunt resistor, please set the current protection level to be equal to or less than the rating of output peak current (Iop). www.onsemi.com 3 STK554U362C-E Module Pin-Out Description Pin Name Description 1 VB3 High Side Floating Supply Voltage 3 2 W, VS3 Output 3 - High Side Floating Supply Offset Voltage 3 - Without pin 4 - Without pin 5 VB2 High Side Floating Supply voltage 2 6 V,VS2 Output 2 - High Side Floating Supply Offset Voltage 7 - Without pin 8 - Without pin 9 VB1 High Side Floating Supply voltage 1 10 U,VS1 Output 1 - High Side Floating Supply Offset Voltage 11 - Without pin 12 - Without pin 13 V+ Positive Bus Input Voltage 14 - Without pin 15 - Without pin 16 ITRIP Current protection pin 17 U- Low Side Emitter Connection - Phase U 18 FLTEN Enable input / Fault output 19 V- Low Side Emitter Connection - Phase V 20 HIN1 Logic Input High Side Gate Driver - Phase U 21 W- Low Side Emitter Connection - Phase W 22 HIN2 Logic Input High Side Gate Driver - Phase V 23 HIN3 Logic Input High Side Gate Driver - Phase W 24 LIN1 Logic Input Low Side Gate Driver - Phase U 25 LIN2 Logic Input Low Side Gate Driver - Phase V 26 LIN3 Logic Input Low Side Gate Driver - Phase W 27 TH Thermistor output 28 VDD +15 V Main Supply 29 VSS Negative Main Supply www.onsemi.com 4 STK554U362C-E Equivalent Block Diagram VB3( 1) W,VS3( 2) VB2( 5) V,VS2( 6) VB1( 9) U,VS1(10) V+ (13) DB DB DB U.V. U.V. U.V. U- (17) V- (19) W- (21) Level Level Level Shifter Shifter Shifter HIN1(20) HIN2(22) HIN3(23) Logic Logic Logic LIN1(24) LIN2(25) LIN3(26) Thermistor TH(27) ITRIP(16) Shutdown VDD(28) VSS(29) Enable/Disable Under voltage + Detect - S Timer Q R Vref Latch time about 2ms FLTEN(18) www.onsemi.com 5 STK554U362C-E Test Circuit The tested phase : U+ shows the upper side of the U phase and U- shows the lower side of the U phase.  ICE / IR(BD) M N U+ 13 10 M N U(BD) 9 29 V+ 13 6 W+ 13 2 V(BD) 5 29 U10 17 V6 19 ICE W2 21 9 M A VD1=15V 10 5 W(BD) 1 29 VD2=15V 6 VCE 1 VD3=15V 2 28 VD4=15V 29 N Fig.1  VCE(SAT) (Test by pulse) M N m U+ 13 10 20 V+ 13 6 22 W+ 13 2 23 U10 17 24 V6 19 25 9 W2 21 26 M VD1=15V 10 5 VD2=15V 6 V Io 1 VD3=15V VCE(SAT) 2 28 VD4=15V 5V m 29 16 Fig.2  VF (Test by pulse) M N U+ 13 10 N V+ 13 6 W+ 13 2 U10 17 V6 19 M W2 21 V N Fig.3  ID M N VD1 9 10 VD2 5 6 VD3 1 2 VD4 28 29 ID A M VD* N Fig.4 www.onsemi.com 6 VF Io STK554U362C-E  Switching time (The circuit is a representative example of the lower side U phase.) 9 Input signal (0 to 5 V) 13 VD1=15V 10 5 VD2=15V 6 90% Io 10 1 Vcc CS VD3=15V 2 28 10% tON VD4=15V tOFF Input signal Io 24 29 16 17 Fig.5  RB-SOA (The circuit is a representative example of the lower side U phase.) Input signal (0 to 5 V) 9 13 VD1=15V 10 5 VD2=15V 6 Io 10 1 Vcc CS VD3=15V 2 28 VD4=15V Input signal Io 24 29 16 17 Fig.6 www.onsemi.com 7 STK554U362C-E Input / Output Timing Chart VBS undervoltage protection reset signal ON HIN1,2,3 OFF LIN1,2,3 *2 VDD VDD undervoltage protection reset voltage *3 VBS undervoltage protection reset voltage VB1,2,3 VIT≥0.54V *4 ITRIP terminal Voltage VIT