Intelligent Power Module
(IPM)
600 V, 30 A
STK581U3C2D-E
Overview
This “Inverter IPM” is highly integrated device containing all High
Voltage (HV) control from HV−DC to 3−phase outputs in a single SIP
module (Single−In line Package). Output stage uses IGBT/FRD
technology and implements Under Voltage Protection (UVP) and
Over Current Protection (OCP) with a Fault Detection output flag.
Internal Boost diodes are provided for high side gate boost drive.
Features
• Single Control Power Supply due to Internal Bootstrap Circuit for
•
•
•
•
•
High Side Pre−driver Circuit
All Control Input and Status Output are at Low Voltage Levels
directly compatible with Microcontrollers
Built−in Cross Conduction Prevention
Externally accessible Embedded Thermistor for Substrate
Temperature Measurement
The Level of the Over−current Protection Current is adjustable with
the External Resistor, “RSD”
These Devices are Pb−Free and are RoHS Compliant
Certification
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SIP22 70x31.1
CASE 127BU
MARKING DIAGRAM
STK581U3C2D
ABCDD
STK581U3C2D = Specific Device Code
A
= Year
B
= Month
C
= Production Site
DD
= Factory Lot code
Device marking is on package underside
• UL1557 (File number : E339285)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
April, 2020 − Rev. 2
1
Publication Order Number:
STK581U3C2D−E/D
STK581U3C2D−E
Specifications
ABSOLUTE MAXIMUM RATINGS (at Tc = 25°C)
Ratings
Unit
Supply voltage
Parameter
VCC
P to N, surge < 500 V (Note 1)
450
V
Collector−emitter voltage
VCE
P to U,V,W or U,V,W to N
600
V
P, N, U,V,W terminal current
±30
A
P, N, U,V,W terminal current at Tc = 100°C
±15
A
P, N, U,V,W terminal current for a Pulse width of 1 ms
±45
A
VB1 to U, VB2 to V, VB3 to W, VDD to VSS (Note 2)
20
V
HIN1, 2, 3, LIN1, 2, 3
−0.3 to VDD
V
FAULT terminal
−0.3 to VDD
V
Output current
Output peak current
Pre−driver voltage
Input signal voltage
FAULT terminal voltage
Symbol
Io
Iop
VD1,2,3,4
VIN
VFAULT
Conditions
Maximum power dissipation
Pd
IGBT per channel
49
W
Junction temperature
Tj
IGBT, FRD
150
°C
Storage temperature
Tstg
−40 to +125
°C
Operating case temperature
Tc
Withstand voltage
−40 to +100
°C
Case mounting screws (Note 3)
1.17
Nm
50 Hz sine wave AC 1 minute (Note 4)
2000
VRMS
IPM case temperature
Tightening torque
Vis
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
NOTE: Reference voltage is “VSS” terminal voltage unless otherwise specified.
1. Surge voltage developed by the switching operation due to the wiring inductance between “P” and “N” terminal.
2. Terminal voltage : VD1 = VB1 to U, VD2 = VB2 to V, VD3 = VB3 to W, VD4 = VDD to VSS
3. Flatness of the heat−sink should be 0.15 mm and below.
4. Test conditions : AC 2500 V, 1 s.
ELECTRICAL CHARACTERISTICS (at Tc = 25_C, VD1, VD2, VD3, VD4 = 15 V, VCC = 300 V, L = 3.5 mH)
Parameter
Symbol
Conditions
Test
Circuit
Min
Typ
Max
Unit
Fig.1
−
−
0.1
mA
−
−
0.1
mA
−
1.8
2.7
V
Power Output Section
Collector−emitter cut−off current
Bootstrap diode reverse current
Collector to emitter
saturation voltage
Diode forward voltage
Junction to case
thermal resistance
ICE
IR(BD)
VCE(SAT)
VF
VCE = 600 V
VR(BD)
Fig.2
Ic = 30 A
Tj = 25°C
Upper side
Lower side
(Note 5)
−
2.1
3.0
Ic = 15 A
Tj = 100°C
Upper side
−
1.5
−
Lower side
(Note 5)
−
1.7
−
IF = 30 A
Tj = 25°C
Upper side
−
2.0
2.9
Lower side
(Note 5)
−
2.3
3.2
IF = 15 A
Tj = 100°C
Upper side
−
1.5
−
Lower side
(Note 5)
−
1.7
−
Fig.3
qj−c(T)
IGBT
−
−
2.5
qj−c(D)
FRD
−
−
3
−
0.08
0.4
−
1.6
4
V
°C/W
Control (Pre−driver) Section
Pre−driver power dissipation
ID
Fig.4
VD1, 2, 3 = 15 V
VD4 = 15 V
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2
mA
STK581U3C2D−E
ELECTRICAL CHARACTERISTICS (at Tc = 25_C, VD1, VD2, VD3, VD4 = 15 V, VCC = 300 V, L = 3.5 mH) (continued)
Parameter
Symbol
Test
Circuit
Conditions
Min
Typ
Max
Unit
2.5
−
−
V
Control (Pre−driver) Section
High level Input voltage
Low level Input voltage
Input threshold voltage hysteresis
(Note 5)
Vin H
Vin L
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3 to VSS
Vinth(hys)
−
−
0.8
V
0.5
0.8
−
V
Logic 1 input leakage current
IIN+
VIN = +3.3 V
−
100
143
mA
Logic 0 input leakage current
IIN−
VIN = 0 V
−
−
2
mA
FAULT terminal input electric
current
IoSD
FAULT : ON / VFAULT = 0.1 V
−
2
−
mA
FAULT clear time
FLTCLR
18
−
80
ms
VCC and VS undervoltage positive
going threshold
VCCUV+
VSUV+
10.5
11.1
11.7
V
VCC and VS undervoltage negative
going threshold
VCCUV−
VSUV−
10.3
10.9
11.5
V
VCC and VS undervoltage
hysteresis
VCCUVH
VSUVH−
0.14
0.2
−
V
38.5
−
48.2
A
0.32
0.34
0.36
V
0.3
0.6
1.3
ms
−
0.9
1.6
−
800
−
mJ
Fault output latch time.
Over current protection level
ISD
PW = 100 ms, RSD = 0 W
Output level for current monitor
ISO
Io = 30 A
tON
Io = 30 A
Fig.5
Switching Characterisitcs
Switching time
Fig.6
tOFF
Turn−on switching loss
Eon
Io = 30 A
Turn−off switching loss
Eoff
−
550
−
mJ
Total switching loss
Etot
−
1350
−
mJ
Turn−on switching loss
Eon
−
530
−
mJ
Turn−off switching loss
Eoff
−
450
−
mJ
Total switching loss
Etot
−
980
−
mJ
Diode reverse recovery energy
Erec
−
24
−
mJ
−
58
−
ns
Diode reverse recovery time
Io = 15 A, Tc = 100°C
IF = 15 A, P = 400 V, Tc = 100°C
trr
Reverse bias safe operating area
RBSOA
Io = 45 A, VCE = 450 V
Short circuit safe operating area
SCSOA
VCE = 400 V, Tc = 100°C
Allowable offset voltage slew rate
dv/dt
Between U, V, W to N
Full square
4
−
−
ms
−50
−
50
V/ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Reference voltage is “VSS” terminal voltage unless otherwise specified.
5. The lower side’s VCE(SAT) and VF include a loss by the shunt resistance
(UVLO : with hysteresis about 0.2 V) is as
follows.
Upper side:
The gate is turned off and will return to regular
operation when recovering to the normal voltage,
but the latch will continue till the input signal will
turn ‘low’.
Lower side:
The gate is turned off and will automatically reset
when recovering to normal voltage. It does not
depend on input signal voltage.
Notes:
1. When the internal protection circuit operates, a
Fault signal is turned ON (When the Fault terminal
is low level, Fault signal is ON state : output form
is open DRAIN) but the Fault signal does not
latch.After protection operation ends,it returns
automatically within about 18 ms to 80 ms and
resumes operation beginning condition. So, after
Fault signal detection, set all input signals to OFF
(Low) at once. However, the operation of
pre−drive power supply low voltage protection
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3
STK581U3C2D−E
2. When assembling the IPM on the heat sink with
M3 type screw, tightening torque range is 0.79 Nm
to 1.17 Nm.
3. The pre−drive low voltage protection is the feature
to protect devices when the pre−driver supply
voltage falls due to an operating malfunction.
RECOMMENDED OPERATING CONDITIONS (at Tc = 25°C)
Item
Symbol
Conditions
Min
Typ
Max
Unit
0
280
450
V
VB1 to U, VB2 to V, VB3 to W
12.5
15
17.5
V
Supply voltage
VCC
P to N
Pre−driver supply voltage
VD1, 2, 3
VD4
VDD to VSS (Note 6)
13.5
15
16.5
ON−state input voltage
VIN(ON)
HIN1, HIN2, HIN3, LIN1, LIN2, LIN3
3.0
−
5.0
OFF−state input voltage
VIN(OFF)
0
−
0.0
PWM frequency
fPWM
1
−
20
kHz
Dead time
DT
Turn−off to turn−on
2
−
−
ms
Allowable input pulse width
PWIN
ON and OFF
1
−
−
ms
0.79
−
1.17
Nm
Package mounting torque
‘M4’ type screw
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Pre−drive power supply (VD4 = 15 ±1.5 V) must have the capacity of Io = 20 mA (DC), 0.5 A (Peak).
MODULE PIN−OUT DESCRIPTION
Pin
Name
1
VB1
Description
2
U, VS1
3
−
4
VB2
5
V,VS2
6
−
7
VB3
8
W,VS3
9
−
Without Pin
10
P
Positive Bus Input Voltage
11
−
Without Pin
12
N
Positive Bus Input Voltage
13
HIN1
Logic Input High Side Gate Driver − Phase U
14
HIN2
Logic Input High Side Gate Driver − Phase V
15
HIN3
Logic Input High Side Gate Driver − Phase W
16
LIN1
Logic Input Low Side Gate Driver − Phase U
17
LIN2
Logic Input Low Side Gate Driver − Phase V
18
LIN3
Logic Input Low Side Gate Driver − Phase W
19
FAULT
20
ISO
Current monitor output
21
VDD
+15V Main Supply
22
VSS
Negative Main Supply
High Side Floating Supply Voltage 1
Output 1 − High Side Floating Supply Offset Voltage
Without Pin
High Side Floating Supply voltage 2
Output 2 − High Side Floating Supply Offset Voltage
Without Pin
High Side Floating Supply voltage 1
Output 1 − High Side Floating Supply Offset Voltage
FAULT Output
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STK581U3C2D−E
Equivalent Block Diagram
VB1(1)
U, VS1(2)
VB2(4)
V, VS2(5)
VB3(7)
W,VS3(8)
BD
BD
BD
U.V.
U.V.
U.V.
P(10)
Shunt Resistor
N(12)
Level
Shifter
Level
Shifter
Level
Shifter
HIN1(13)
HIN2(14)
HIN3(15)
Logic
Logic
Logic
LIN1(16)
LIN2(17)
LIN3(18)
FAULT(19)
ISO(20)
(Protection)
VDD(21)
VSS(22)
Shut down
Thermistor
VDD−Under Voltage
Figure 1. Block Diagram
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5
Latch time About 30ms
(Automatic reset)
STK581U3C2D−E
Test Circuits
(The tested phase : U+ shows the upper side of the U phase
and U− shows the lower side of the U phase.)
• ICE / IR(BD)
U+
V+
W+
U−
M
10
10
10
2
5
8
N
2
5
8
12
12
12
U(DB)
V(DB)
W(DB)
M
1
4
7
N
22
22
22
V−
W−
Figure 2. Test Circuit for ICE
• VCE(SAT) (Test by pulse)
U+
V+
W+
U−
V−
W−
M
10
10
10
2
6
8
N
2
5
8
12
12
12
m
13
14
15
16
17
18
Figure 3. Test Circuit for VCE(sat)
• VF (Test by pulse)
U+
V+
W+
U−
V−
W−
M
10
10
10
2
5
8
N
2
5
8
12
12
12
Figure 4. Test Circuit for VF
• ID
VD1
VD2
VD3
VD4
M
1
4
7
21
N
2
5
8
22
Figure 5. Test Circuit for ID
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6
STK581U3C2D−E
• ISD
Input signal
(0 to 5V)
ISD
IO
100 m s
Figure 6. Test Circuit for ISD
• Switching time
(The circuit is a representative example of the lower side U phase.)
Input signal
(0 to 5V)
90%
IO
10%
tON
tOFF
Figure 7. Switching Time Test Circuit
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STK581U3C2D−E
Logic Timing Chart
VBS undervoltage protection reset signal
ON
HIN1,2,3
OFF
LIN1,2,3
VDD undervoltage protection reset voltage
*2
VDD
*3
VBS undervoltage protection reset voltage
VB1,2,3
*4
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−−−−
−−−−−−−−−−−−−−−−−−−−
ISD operation current level−−−−−−−−−−
−−−−−−−−−−−
−−−−−
−−−−−−−−−−−−−−−−−−−
−terminal
(BUS line)
Current
FAULT terminal
Voltage
(at pulled−up)
ON
*1
Upper
U, V, W
OFF
*1
Lower
U ,V, W
Automatically reset after protection
(18ms to 80ms)
Notes:
*1: Diagram shows the prevention of shoot−through via control logic. More dead time to account for switching delay needs to be added
externally.
*2: When VDD decreases all gate output signals will go low and cut off all of 6 IGBT outputs. When VDD rises the operation will resume
immediately.
*3: When the upper side gate voltage at VB1, VB2 and VB3 drops only, the corresponding upper side output is turned off. The outputs
return to normal operation immediately after the upper side gate voltage rises.
*4: In case of over current detection, all IGBT’s are turned off and the FAULT output is asserted. Normal operation resumes in 18 to
80 ms after the over current condition is removed.
Figure 8. Logic Timing Chart
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STK581U3C2D−E
Logic Level Table
LOGIC LEVEL TABLE
INPUT
P
Ho
OUTPUT
HIN
LIN
OCP
Ho
Lo
U, V, W
FAULT
H
L
OFF
H
L
P
OFF
L
H
OFF
L
H
N
OFF
L
L
OFF
L
L
High
Impedance
OFF
H
H
OFF
L
L
High
Impedance
OFF
X
X
ON
L
L
High
Impedance
ON
HIN 1,2,3
(13, 14, 15)
IC
U,V,W
Driver
(2,5,8)
LIN 1,2,3
(16 ,17 ,18)
Lo
N
Figure 9.
Sample Application Circuit
Figure 10. Sample Application Circuit
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STK581U3C2D−E
Usage Precautions
4. “FAULT” (pin19) is open DRAIN output terminal
(Active Low). Pull up resistor is recommended
more than 5.6 kW.
5. Inside the IPM, a thermistor used as the
temperature monitor for internal substrate is
connected between VSS terminal and TH terminal,
therefore, an external pull up resistor connected
between the TH terminal and an external power
supply should be used. The temperature monitor
example application is as follows, please refer the
Fig.11, and Fig.12 below.
6. Pull down resistor of 33 kW is provided internally
at the signal input terminals. An external resistor
of 2.2 k to 3.3 kW should be added to reduce the
influence of external wiring noise.
7. The over−current protection feature is not intended
to protect in exceptional fault condition. An
external fuse is recommended for safety.
8. When input pulse width is less than 1.0 ms, an
output may not react to the pulse. (Both ON signal
and OFF signal)
1. This IPM includes bootstrap diode and resistors.
Therefore, by adding a capacitor “CB”, a high side
drive voltage is generated; each phase requires an
individual bootstrap capacitor. The recommended
value of CB is in the range of 1 to 47 mF, however
this value needs to be verified prior to production.
If selecting the capacitance more than 47 mF
(±20%), connect a resistor (about 20 W) in series
between each 3−phase upper side power supply
terminals (VB1, 2, 3) and each bootstrap capacitor.
When not using the bootstrap circuit, each upper
side pre−drive power supply requires an external
independent power supply.
2. It is essential that wirning length between
terminals in the snubber circuit be kept as short as
possible to reduce the effect of surge voltages.
Recommended value of “CS” is in the range of 0.1
to 10 mF.
3. “ISO” (pin20) is terminal for current monitor.
When the pull−down resistor is used, please select
it more than 5.6 kW
This data shows the example of the application circuit,
does not guarantee a design as the mass production set.
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STK581U3C2D−E
THERMISTOR CHARACTERISTICS
Parameter
Resistance
B−Constant (25 to 50°C)
Symbol
Condition
Min
Typ
Max
Unit
R25
Tc = 25°C
99
100
101
kW
R100
Tc = 100°C
5.12
5.38
5.66
kW
4165
4250
4335
K
−40
−
+125
°C
B
Temperature Range
Figure 11. Thermistor Resistance versus Case Temperature
Condition
Pull− up resisto r = 39kW
Pull− up voltage of TH = 5V
Figure 12. Thermistor Voltage versus Case Temperature
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11
STK581U3C2D−E
PWM Switching Frequency Characteristics
Maximum sinusoidal phase current as function of
switching frequency (VBUS = 300 V, Tc = 100°C)
Figure 13. PWM Switching Frequency Characteristics
Switching Waveforms
IGBT Turn−on. Typical turn−on waveform @Tc = 100°C, VBUS = 400 V
Turn on
X (200 ns/div)
VCE (100 V/div)
Io (10 A/div)
Figure 14.
IGBT Turn−off. Typical turn−off waveform @Tc = 100°C, VBUS = 400 V
X (200 ns/div)
Io (10 A/div)
Turn off
VCE (100 V/div)
Figure 15.
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12
STK581U3C2D−E
CB Capacitor Value Calculation for Bootstrap Circuit
CALCULATE CONDITIONS TABLE
Item
Symbol
Value
Unit
VBS
15
V
Total gate charge of output power IGBT at 15 V.
Qg
266
nC
Upper side power supply low voltage protection.
UVLO
12
V
IDmax
400
mA
Tonmax
−
s
Upper side power supply.
Upper side power dissipation.
ON time required for CB voltage to fall from 15 V to UVLO
Capacitance Calculation Formula
CB must not be discharged below to the upper limit of the
UVLO − the maximum allowable on−time (Tonmax) of the
upper side is calculated as follows:
VBS * CB – Qg – IDmax * Tonmax = UVLO * CB
CB = (Qg + IDmax * Tonmax) / (VBS – UVLO)
The relationship between Tonmax and CB becomes as
follows. CB is recommended to be approximately 3 times
the value calculated above. The recommended value of CB
is in the range of 1 to 47 mF, however, the value needs to be
verified prior to production.
Figure 16. Tonmax−CB Characteristics
ORDERING INFORMATION
Device
Marking
Package
Shipping
STK581U3C2D−E
STK581U3C2D
SIP22 70x31.1
(Pb−Free)
7 Units / Tube
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SIP22 70x31.1
CASE 127BU
ISSUE O
DATE 30 APR 2012
Missing P in : 3,6,9,11
70
4.6
6
31.1
2−R 2.3
2.5
8C F 00
1
( 16)
S IP 3
21×2.54＝53.34
0.5
.2
0.75+0
−0.05
2.54
. 2
0.5+0
− 0.05
22
12.5
3.5±
0.4
2−2
58
78
DOCUMENT NUMBER:
98AON79787E
DESCRIPTION:
SIP22 70X31.1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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