SZESD7462N2T5G

DATA SHEET www.onsemi.com ESD Protection Diode Ultra−Low Capacitance Micro−Packaged Diodes for ESD Protection ESD7462, SZESD7462 MARKING DIAGRAM The ESD7462 is designed to protect voltage sensitive components that require ultra−low capacitance from ESD and transient voltage events. It has industry leading capacitance linearity over voltage making it ideal for RF applications. This capacitance linearity combined with the extremely small package and low insertion loss makes this part well suited for use in antenna line applications for wireless handsets and terminals. X2DFN2 CASE 714AB 4 M = Specific Device Code = Date Code Features • • • • • • • • • Industry Leading Capacitance Linearity Over Voltage Ultra−Low Capacitance: 0.3 pF Typ Insertion Loss: 0.05 dB at 1 GHz; 0.10 dB at 3 GHz Low Leakage: < 1 nA Typ Protection for the following IEC Standards: ♦ IEC61000−4−2 (ESD): Level 4 ♦ IEC61000−4−4 (EFT): 40 A −5/50 ns ♦ IEC61000−4−5 (Lightning): 1 A (8/20 ms) Protection for ISO 10605 (ESD) SZESD7462MXWT5G − Wettable Flank Package for Optimal Automated Optical Inspection (AOI) SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • • • • RF Signal ESD Protection RF Switching, PA, and Antenna ESD Protection Near Field Communications USB 2.0, USB 3.0 X2DFNW2 CASE 711BG E M 4M EM = Specific Device Code = Date Code ORDERING INFORMATION Package Shipping† ESD7462N2T5G X2DFN2 (Pb−Free) 8000 / Tape & Reel SZESD7462N2T5G X2DFN2 (Pb−Free) 8000 / Tape & Reel SZESD7462MXWT5G X2DFNW2 (Pb−Free) 8000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Symbol Value Unit Total Power Dissipation (Note 2) @ TA = 25°C Thermal Resistance, Junction−to−Ambient °PD° RqJA 300 400 mW °C/W TJ, Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Second Duration) TL 260 °C IEC 61000−4−2 Contact (Note 1) IEC 61000−4−2 Air ISO 10605 Contact (330 pF / 330 W) ISO 10605 Contact (330 pF / 2 kW) ISO 10605 Contact (150 pF / 2 kW) Human Body Model (HBM) ESD ±18 ±18 ±13 ±29 ±30 ±8 kV Junction and Storage Temperature Range Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−2 waveform. 2. Mounted with recommended minimum pad size, DC board FR−4 © Semiconductor Components Industries, LLC, 2016 January, 2023 − Rev. 5 1 Publication Order Number: ESD7462/D ESD7462, SZESD7462 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP IR VBR IT I Parameter Symbol VRWM IPP IT VC VBR VRWM IR IR VRWM VBR VC IT Working Peak Reverse Voltage V Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT IPP Test Current Bi−Directional *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol VRWM VBR Parameter Condition Min Typ Reverse Working Voltage 16.5 22 Max Unit 16 V 28 V 100 nA Breakdown Voltage IT = 1 mA (Note 3) IR Reverse Leakage Current VRWM = 5 V VC Clamping Voltage IEC 61000−4−2, ±8 kV Contact See Figures 7 and 8 V VC Clamping Voltage, TLP (Note 4) IPP = ±8 A IPP = ±16 A ±34 ±47 V RDYN Dynamic Resistance TLP Pulse 1.6 W CJ Junction Capacitance VR = 0 V, f = 1 MHz VR = 0 V, f = 1 GHz 0.30 0.25 Insertion Loss f = 1 GHz f = 3 GHz 0.05 0.10 0.55 0.55 pF dB Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1. 4. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. www.onsemi.com 2 ESD7462, SZESD7462 1.E−03 0.55 1.E−04 0.50 1.E−05 0.45 CAPACITANCE (pF) CURRENT (A) TYPICAL CHARACTERISTICS 1.E−06 1.E−07 1.E−08 1.E−09 1.E−10 1.E−11 f = 1 MHz 0.40 0.35 0.30 0.25 0.20 0.15 0.10 1.E−12 1.E−13 −24 −16 0 −8 8 0.05 0 −10 24 16 −6 −2 2 6 VOLTAGE (V) BIAS VOLTAGE (V) Figure 1. Typical IV Characteristic Curve Figure 2. Typical CV Characteristic Curve 1E−08 10 100 POWER DISSIPATION (%) IL, LEAKAGE CURRENT (A) 150°C 1E−09 85°C 1E−10 +55°C 25°C 1E−11 80 60 40 20 −55°C 1E−12 1 3 2 4 5 6 7 8 0 0 9 10 11 12 13 14 15 16 25 50 75 100 TEMPERATURE (°C) VR, REVERSE BIAS VOLTAGE (V) 32 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 VClamp (V) % OF PEAK PULSE CURRENT 90 35 PEAK VALUE IRSM @ 8 ms tr HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 150 Figure 4. Steady State Power Derating Figure 3. IR vs. Temperature Characteristics 100 125 29 IO−GND 26 23 10 0 0 20 40 t, TIME (ms) 60 20 80 0 1 2 Ipk (A) 3 Figure 6. Clamping Voltage vs. Peak Pulse Current (8/20 ms) Figure 5. 8 X 20 ms Pulse Waveform www.onsemi.com 3 4 ESD7462, SZESD7462 180 20 160 0 140 −20 120 VOLTAGE (V) VOLTAGE (V) TYPICAL CHARACTERISTICS 100 80 60 40 −80 −100 −140 0 −20 −25 0 25 50 75 100 125 150 −160 −25 175 25 50 75 100 125 150 175 TIME (ns) Figure 7. Typical IEC61000−4−2 +8 kV Contact ESD Clamping Voltage Figure 8. Typical IEC61000−4−2 −8 kV Contact ESD Clamping Voltage 1 0.55 0 0.50 −1 0.45 −2 0.40 −3 −4 −5 −6 −7 0.35 0.25 0.20 0.15 0.10 −9 −10 0.05 0 1.E+07 1.E+08 1.E+09 1.E+10 VR = 0 V 0.30 −8 0.0E+00 1.0E+09 2.0E+09 3.0E+09 FREQUENCY (Hz) FREQUENCY (Hz) Figure 9. Typical Insertion Loss Figure 10. Typical Capacitance Over Frequency 10 20 −20 18 −10 −18 8 −16 6 10 4 8 6 TLP CURRENT (A) 12 −14 −12 −6 −4 2 0 0 0 −2 0 50 60 −4 −8 2 20 30 40 VC, CLAMPING VOLTAGE (V) −6 −10 4 10 −8 EQUIVALENT VIEC (kV) EQUIVALENT VIEC (kV) 16 14 −2 0 Figure 11. Typical Positive TLP IV Curve NOTE: 0 TIME (ns) CAPACITANCE (pF) S21 (dB) −60 −120 20 TLP CURRENT (A) −40 −10 −20 −50 −30 −40 VC, CLAMPING VOLTAGE (V) 0 −60 Figure 12. Typical Negative TLP IV Curve TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description below for more information. www.onsemi.com 4 ESD7462, SZESD7462 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 13. IEC61000−4−2 Spec Device ESD Gun Under Oscilloscope Test 50 W 50 W Cable Figure 14. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger www.onsemi.com 5 ESD7462, SZESD7462 Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 15. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 16 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. 50 W Coax Cable S Attenuator ÷ 50 W Coax Cable 10 MW IM VM DUT VC Oscilloscope Figure 15. Simplified Schematic of a Typical TLP System Figure 16. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS X2DFNW2 1.0x0.6, 0.65P CASE 711BG ISSUE C SCALE 8:1 DATE 13 SEP 2019 GENERIC MARKING DIAGRAM* XXM XX = Specific Device Code M = Date Code *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G”, may or not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON15241G X2DFNW2 1.0X0.6, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS X2DFN2 1.0x0.6, 0.65P CASE 714AB ISSUE B DATE 21 NOV 2017 SCALE 8:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. EXPOSED COPPER ALLOWED AS SHOWN. 0.10 C A B D É PIN 1 INDICATOR E DIM A A1 b D E e L 0.05 C TOP VIEW A NOTE 3 0.10 C 0.10 C A1 C SIDE VIEW GENERIC MARKING DIAGRAM* SEATING PLANE XX M e b e/2 MILLIMETERS MIN NOM MAX 0.34 0.37 0.40 −−− 0.03 0.05 0.45 0.50 0.55 0.95 1.00 1.05 0.55 0.60 0.65 0.65 BSC 0.20 0.25 0.30 0.05 M XX = Specific Device Code M = Date Code C A B RECOMMENDED SOLDER FOOTPRINT* 1 2X L 0.05 M C A B BOTTOM VIEW 1.20 2X 0.47 2X 0.60 PIN 1 DIMENSIONS: MILLIMETERS *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON98172F X2DFN2 1.0X0.6, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative