SZNUP1105LT1G

NUP1105LT1G, SZNUP1105LT1G ESD Protection Diode Single Line CAN/LIN Bus Protector The NUP1105L has been designed to protect LIN and single line CAN transceivers from ESD and other harmful transient voltage events. This device provides bidirectional protection for the data line with a single SOT−23 package, giving the system designer a low cost option for improving system reliability and meeting stringent EMI requirements. www.onsemi.com SOT−23 BIDIRECTIONAL VOLTAGE SUPPRESSOR 350 W PEAK POWER Features • • • • • • • • • SOT−23 Package Allows One Separate Bidirectional Configuration 350 W Peak Power Dissipation per Line (8 x 20 msec Waveform) Low Reverse Leakage Current (< 100 nA) IEC Compatibility: − IEC 61000−4−2 (ESD): Level 4 − IEC 61000−4−4 (EFT): 40 A – 5/50 ns − IEC 61000−4−5 (Lighting) 8.0 A (8/20 ms) ISO 7637−1, Nonrepetitive EMI Surge Pulse TBD ISO 7637−3, Repetitive Electrical Fast Transient (EFT) TBD EMI Surge Pulses Flammability Rating UL 94 V−0 SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant 1 3 2 • Automotive Electronics PIN 1. ANODE 2. ANODE 3. CATHODE MARKING DIAGRAM 27HMG G 1 27H M G Applications = Device Code = Date Code = Pb−Free Package (Note: Microdot may be in either location) LIN Bus ♦ Single Line CAN Industrial Control Networks ♦ Smart Distribution Systems (SDS®) ♦ DeviceNet™ ♦ • SOT−23 CASE 318 STYLE 27 ORDERING INFORMATION Package Shipping† NUP1105LT1G SOT−23 (Pb−Free) 3,000 / Tape & Reel SZNUP1105LT1G SOT−23 (Pb−Free) 3,000 / Tape & Reel NUP1105LT3G SOT−23 (Pb−Free) 10,000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2004 October, 2017 − Rev. 7 1 Publication Order Number: NUP1105L/D NUP1105LT1G, SZNUP1105LT1G MAXIMUM RATINGS (TJ = 25°C, unless otherwise specified) Symbol PPK Rating Value Peak Power Dissipation 8 x 20 ms Double Exponential Waveform (Note 1) Unit W 350 TJ Operating Junction Temperature Range −55 to 150 °C TJ Storage Temperature Range −55 to 150 °C TL Lead Solder Temperature (10 s) 260 °C Human Body model (HBM) Machine Model (MM) IEC 61000−4−2 Specification (Contact) 16 400 30 kV V kV ESD Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Non-repetitive current pulse per Figure 1. ELECTRICAL CHARACTERISTICS (TJ = 25°C, unless otherwise specified) Symbol VRWM Parameter Test Conditions Reverse Working Voltage (Note 2) Breakdown Voltage IT = 1 mA (Note 3) IR Reverse Leakage Current VRWM = 24 V VC Clamping Voltage VC VBR Min Typ Max 24 Unit V 25.7 28.4 V 100 nA IPP = 5 A (8 x 20 ms Waveform) (Note 4) 40 V Clamping Voltage IPP = 8 A (8 x 20 ms Waveform) (Note 4) 44 V IPP Maximum Peak Pulse Current 8 x 20 ms Waveform (Note 4) 8.0 A CJ Capacitance VR = 0 V, f = 1 MHz (Anode to GND) VR = 0 V, f = 1 MHz (Anode to Anode) 60 30 pF 15 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Surge protection devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 3. VBR is measured at pulse test current IT. 4. Pulse waveform per Figure 1. 5. Include SZ-prefix devices where applicable. www.onsemi.com 2 NUP1105LT1G, SZNUP1105LT1G TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) % OF PEAK PULSE CURRENT WAVEFORM PARAMETERS tr = 8 ms td = 20 ms 90 80 c−t 70 IPP, PEAK PULSE CURRENT (A) 12.0 110 100 60 td = IPP/2 50 40 30 20 10 0 0 10 5 20 15 8.0 6.0 4.0 2.0 0.0 30 25 PULSE WAVEFORM 8 x 20 ms per Figure 1 10.0 25 30 45 50 Figure 2. Clamping Voltage vs Peak Pulse Current Figure 1. Pulse Waveform, 8 × 20 ms 30 45 40 29 35 28 VZ, (V) 30 25 20 VZ 27 26 15 10 25 5 −10 40 90 140 24 −60 190 −10 40 90 140 190 TEMPERATURE (°C) TEMPERATURE (°C) Figure 3. Typical Leakage vs. Temperature Figure 4. Typical VZ @ 1.0 mA vs. Temperature 60 25°C 50 CAPACITANCE (pF) IR, (nA) 40 VC, CLAMPING VOLTAGE (V) t, TIME (ms) 0 −60 35 40 30 20 10 0 0 5 10 15 20 VBIAS Figure 5. Capacitance vs. VBIAS www.onsemi.com 3 25 NUP1105LT1G, SZNUP1105LT1G APPLICATIONS SECTION The NUP1105L provides a surge protection solution for the LIN data communication bus. The NUP1105L is a dual bidirectional surge protection device in a compact SOT−23 package. This device is based on Zener technology that optimizes the active area of a PN junction to provide robust protection against transient EMI surge voltage and ESD. The NUP1105L has been tested to EMI and ESD levels that exceed the specifications of popular high speed LIN networks. VBattery = 8 to 18 V Voltage Regulator Receiver The NUP1105L device can be used to provide transcient voltage suppression for a single data line CAN system. Figure 7 provides an example of a single data line CAN protection circuit. CAN Transceiver NUP1105L Figure 7. High−Speed and Fault Tolerant CAN Surge Protection Circuit VOUT = 5 V LIN Bus Transmitter LIN Transceiver CAN_Data_Line NUP1105L Figure 6. LIN Transceiver SDS is a registered trademark of Honeywell International Inc. DeviceNet is a trademark of Rockwell Automation. www.onsemi.com 4 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−23 (TO−236) CASE 318 ISSUE AT DATE 01 MAR 2023 SCALE 4:1 GENERIC MARKING DIAGRAM* XXXMG G 1 XXX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42226B SOT−23 (TO−236) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−23 (TO−236) CASE 318 ISSUE AT DATE 01 MAR 2023 STYLE 1 THRU 5: CANCELLED STYLE 6: PIN 1. BASE 2. EMITTER 3. COLLECTOR STYLE 7: PIN 1. EMITTER 2. BASE 3. COLLECTOR STYLE 9: PIN 1. ANODE 2. ANODE 3. CATHODE STYLE 10: PIN 1. DRAIN 2. SOURCE 3. GATE STYLE 11: STYLE 12: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. CATHODE 3. CATHODE−ANODE 3. ANODE STYLE 15: PIN 1. GATE 2. CATHODE 3. ANODE STYLE 16: PIN 1. ANODE 2. CATHODE 3. CATHODE STYLE 17: PIN 1. NO CONNECTION 2. ANODE 3. CATHODE STYLE 18: STYLE 19: STYLE 20: PIN 1. CATHODE PIN 1. NO CONNECTION PIN 1. CATHODE 2. CATHODE 2. ANODE 2. ANODE 3. ANODE 3. CATHODE−ANODE 3. GATE STYLE 21: PIN 1. GATE 2. SOURCE 3. DRAIN STYLE 22: PIN 1. RETURN 2. OUTPUT 3. INPUT STYLE 23: PIN 1. ANODE 2. ANODE 3. CATHODE STYLE 24: PIN 1. GATE 2. DRAIN 3. SOURCE STYLE 27: PIN 1. CATHODE 2. CATHODE 3. CATHODE STYLE 28: PIN 1. ANODE 2. ANODE 3. ANODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42226B SOT−23 (TO−236) STYLE 8: PIN 1. ANODE 2. NO CONNECTION 3. CATHODE STYLE 13: PIN 1. SOURCE 2. DRAIN 3. GATE STYLE 25: PIN 1. ANODE 2. CATHODE 3. GATE STYLE 14: PIN 1. CATHODE 2. GATE 3. ANODE STYLE 26: PIN 1. CATHODE 2. ANODE 3. NO CONNECTION Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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