SM12T1
ESD Protection Diode Array
Dual Common Anode
Specification Features:
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PIN 1. CATHODE
2. CATHODE
3. ANODE
1
3
2
• SOT−23 Package Allows Either Two Separate Unidirectional
•
•
•
•
•
Configurations or a Single Bidirectional Configuration
Working Peak Reverse Voltage Range − 12 V
Standard Zener Breakdown Voltage Range − 13.3 V to 15.75 V
Peak Power − 300 Watt (8 X 20 ms)
Low Leakage
Flammability Rating UL 94 V−0
Mechanical Characteristics:
CASE: Void-free, transfer-molded, thermosetting plastic case
FINISH: Corrosion resistant finish, easily solderable
MAXIMUM CASE TEMPERATURE FOR SOLDERING PURPOSES:
260°C for 10 Seconds
Package designed for optimal automated board assembly
Small package size for high density applications
Available in 8 mm Tape and Reel
MARKING
DIAGRAM
3
1
2
12M
SOT−23
CASE 318
STYLE 12
M
These dual monolithic silicon zener diodes are designed for
applications requiring transient overvoltage protection capability. They
are intended for use in voltage and ESD sensitive equipment such as
computers, printers, business machines, communication systems,
medical equipment and other applications. Their dual junction common
anode design protects two separate lines using only one package. These
devices are ideal for situations where board space is at a premium.
12M = Device Code
M
= Date Code
ORDERING INFORMATION
Device
SM12T1
Package
Shipping
SOT−23
3000/Tape & Reel
Use the Device Number to order the 7 inch/3,000 unit reel.
Replace the “T1” with “T3” in the Device Number to order the
13 inch/10,000 unit reel.
© Semiconductor Components Industries, LLC, 2001
November, 2017 − Rev. 1
1
Publication Order Number:
SM12T1/D
SM12T1
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Ppk
300
Watts
±15
±8.0
kV
IEC 61000−4−4 (EFT)
40
A
IEC 61000−4−5 (Lightening)
12
A
Peak Power Dissipation @ 20 ms (Note 1)
@ TL ≤ 25°C
IEC 61000−4−2 (ESD)
Air
Contact
Total Power Dissipation on FR−5 Board (Note 2) @ TA = 25°C
Derate above 25°C
°PD°
225
1.8
°mW°
mW/°C
Thermal Resistance Junction to Ambient
RθJA
556
°C/W
Total Power Dissipation on Alumina Substrate (Note 3) @ TA = 25°C
Derate above 25°C
°PD°
300
2.4
°mW
mW/°C
Thermal Resistance Junction to Ambient
RθJA
417
°C/W
Junction and Storage Temperature Range
TJ, Tstg
− 55 to +150
°C
TL
260
°C
Lead Solder Temperature − Maximum (10 Second Duration)
1. Non−repetitive current pulse per Figure 3
2. FR−5 = 1.0 x 0.75 x 0.62 in.
3. Alumina = 0.4 x 0.3 x 0.024 in., 99.5% alumina
*Other voltages may be available upon request
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
UNIDIRECTIONAL (Circuit tied to Pins 1 and 3 or 2 and 3)
Parameter
Symbol
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
VBR
IT
QVBR
I
IF
Working Peak Reverse Voltage
Maximum Reverse Leakage Current @ VRWM
Breakdown Voltage @ IT
VC VBR VRWM
V
IR VF
IT
Test Current
Maximum Temperature Coefficient of VBR
IF
Forward Current
VF
Forward Voltage @ IF
ZZT
Maximum Zener Impedance @ IZT
IZK
Reverse Current
ZZK
Maximum Zener Impedance @ IZK
IPP
Uni−Directional
ELECTRICAL CHARACTERISTICS
VBR, Breakdown Voltage
Device
Device
Marking
IR @ VRWM
(Volts)
(mA)
Min
SM12T1
12M
12
1.0
13.3
Typical Capacitance
VC @
IPP = 1 Amp
Max IPP
(Note 4)
Max
(Volts)
(Amps)
Pin 1 to 3 @ 0 Volts
15.75
19
12
95
(Volts)
VRWM
4. 8 × 20 ms pulse waveform per Figure 3
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2
(pF)
SM12T1
TYPICAL CHARACTERISTICS
300
PD, POWER DISSIPATION (mW)
PPP, PEAK PULSE POWER (kW)
10
1
0.1
0.01
0.1
1
100
10
tp, PULSE DURATION (ms)
250
150
100
Figure 1. Non−Repetitive Peak Pulse Power
versus Pulse Time
70
60
50
HALF VALUE IRSM/2 @ 20 ms
40
30
tP
20
75
100
125
TEMPERATURE (°C)
150
80
70
60
50
40
30
20
10
10
0
50
90
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
80
25
100
PEAK VALUE IRSM @ 8 ms
tr
90
0
Figure 2. Steady State Power Derating Curve
C, CAPACITANCE (pF)
% OF PEAK PULSE CURRENT
100
FR−5 BOARD
50
0
1000
ALUMINA SUBSTRATE
200
0
20
40
60
0
80
t, TIME (ms)
0
1
5
8
BIAS VOLTAGE (VOLTS)
Figure 4. Typical Diode Capacitance
Figure 3. 8 × 20 ms Pulse Waveform
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3
12
175
SM12T1
TYPICAL COMMON ANODE APPLICATIONS
A quad junction common anode design in a SOT−23
package protects four separate lines using only one package.
This adds flexibility and creativity to PCB design especially
when board space is at a premium. Two simplified examples
of surge protection applications are illustrated below.
Computer Interface Protection
A
KEYBOARD
TERMINAL
PRINTER
ETC.
B
C
I/O
D
FUNCTIONAL
DECODER
GND
SM12T1
Microprocessor Protection
VDD
VGG
ADDRESS BUS
RAM
ROM
DATA BUS
CPU
I/O
SM12T1
CLOCK
CONTROL BUS
GND
SM12T1
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4
SM12T1
INFORMATION FOR USING THE SOT−23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
inches
mm
SOT−23
SOT−23 POWER DISSIPATION
SOLDERING PRECAUTIONS
The power dissipation of the SOT−23 is a function of the
drain pad size. This can vary from the minimum pad size
for soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from
the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data
sheet for the SOT−23 package, PD can be calculated as
follows:
PD =
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
TJ(max) − TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 225 milliwatts.
PD = 150°C − 25°C = 225 milliwatts
556°C/W
The 556°C/W for the SOT−23 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 225
milliwatts. There are other alternatives to achieving higher
power dissipation from the SOT−23 package. Another
alternative would be to use a ceramic substrate or an
aluminum core board such as Thermal Clad®. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
Thermal Clad is a registered trademark of the Bergquist Company
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318
ISSUE AT
DATE 01 MAR 2023
SCALE 4:1
GENERIC
MARKING DIAGRAM*
XXXMG
G
1
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42226B
SOT−23 (TO−236)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318
ISSUE AT
DATE 01 MAR 2023
STYLE 1 THRU 5:
CANCELLED
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 7:
PIN 1. EMITTER
2. BASE
3. COLLECTOR
STYLE 9:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 10:
PIN 1. DRAIN
2. SOURCE
3. GATE
STYLE 11:
STYLE 12:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. CATHODE
3. CATHODE−ANODE
3. ANODE
STYLE 15:
PIN 1. GATE
2. CATHODE
3. ANODE
STYLE 16:
PIN 1. ANODE
2. CATHODE
3. CATHODE
STYLE 17:
PIN 1. NO CONNECTION
2. ANODE
3. CATHODE
STYLE 18:
STYLE 19:
STYLE 20:
PIN 1. CATHODE
PIN 1. NO CONNECTION PIN 1. CATHODE
2. CATHODE
2. ANODE
2. ANODE
3. ANODE
3. CATHODE−ANODE
3. GATE
STYLE 21:
PIN 1. GATE
2. SOURCE
3. DRAIN
STYLE 22:
PIN 1. RETURN
2. OUTPUT
3. INPUT
STYLE 23:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 24:
PIN 1. GATE
2. DRAIN
3. SOURCE
STYLE 27:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
STYLE 28:
PIN 1. ANODE
2. ANODE
3. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42226B
SOT−23 (TO−236)
STYLE 8:
PIN 1. ANODE
2. NO CONNECTION
3. CATHODE
STYLE 13:
PIN 1. SOURCE
2. DRAIN
3. GATE
STYLE 25:
PIN 1. ANODE
2. CATHODE
3. GATE
STYLE 14:
PIN 1. CATHODE
2. GATE
3. ANODE
STYLE 26:
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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