TCP-3027HA-QT

TCP-3027HA High Linearity 2.7 pF Passive Tunable Integrated Circuits (PTIC) Introduction www.onsemi.com ON Semiconductor’s PTICs have excellent RF performance and power consumption, making them suitable for any mobile handset or radio application. The fundamental building block of our PTIC product line is a tunable material called ParaScant, based on Barium Strontium Titanate (BST). PTICs have the ability to change their capacitance from a supplied bias voltage generated by the Control IC. TCP−3027HA has improved linearity for use in applications where lower harmonic performance is required. The 2.7 pF high linearity PTICs are available in QFN packages for easy mounting directly on printed circuit boards. QFN6 1.6x1.2 CASE 485DX MARKING DIAGRAM Key Features • • • • • • • • High Tuning Range and Operation up to 20 V Usable Frequency Range: from 700 MHz to 2.7 GHz High Quality Factor (Q) for Low Loss High Power Handling Capability Compatible with PTIC Control IC TCC-103, TCC−206 QFN Package: 1.200 x 1.600 x 0.950 mm QFN: MSL−2 Moisture Sensitivity Level (per J−STD−020) These devices are Pb−Free and RoHS Compliant X.XA X.X = 2.7 A = High Linearity FUNCTIONAL BLOCK DIAGRAM PTIC Typical Applications • • • • Multi-band, Multi-standard, Advanced and Simple Mobile Phones Tunable Antenna Matching Networks Tunable RF Filters Active Antennas RF1 RF2 Bias PTIC Functional Block Diagram ORDERING INFORMATION Device Package Shipping† TCP−3027HA−QT QFN6 (Pb−Free) 8000 Units / 13“ Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2015 August, 2015 − Rev. 2 1 Publication Order Number: TCP−3027HA/D TCP−3027HA DC Bias 1 A1 A2 NC RF2 B1 B2 RF1 RF2 C1 C2 RF1 Figure 1. PTIC Functional Block Diagram (Top Level View) Table 1. SIGNAL DESCRIPTIONS Ball / Pad Number Pin Name A1 DC Bias 1 DC Bias Voltage Description B1 RF2 RF Input / Output C1 RF2 RF Input / Output A2 NC Not Connected B2 RF1 RF Input / Output C2 RF1 RF Input / Output www.onsemi.com 2 TCP−3027HA TYPICAL SPECIFICATIONS Representative Performance Data at 255C Table 2. PERFORMANCE DATA Parameter Min Operating Bias Voltage Typ 2.0 Units 20 V Capacitance (Vbias = 2 V) 2.43 2.70 2.97 pF Capacitance (Vbias = 20 V) 0.621 0.675 0.729 pF Tuning Range (2 V - 20 V) 3.60 4.00 4.50 Leakage Current (WLCSP) Operating Frequency 700 Quality Factor @ 700 MHz, 10 V Quality Factor @ 2.4 GHz, 10 V IP3 (Vbias = 2 V) [5] [5] [1,3] IP3 (Vbias = 20 V) [1,3] 2nd Harmonic (Vbias = 20 V) 3rd Harmonic (Vbias = 2 V) mA 2700 MHz 60 30 35 70 72 dBm 80 82 dBm −65 dBm −70 dBm −50 dBm [2,3] [2,3] 3rd Harmonic (Vbias = 20 V) 2.0 55 2nd Harmonic (Vbias = 2 V) [2,3] [2,3] −70 dBm [4] 80 ms Transition Time (Cmax ³ Cmin) [4] 70 ms Transition Time (Cmin ³ Cmax) 1. 2. 3. 4. 5. Max f1 = 850 MHz, f2 = 860 MHz, Pin 25 dBm/Tone 850 MHz, Pin +34 dBm IP3 and Harmonics are measured in the shunt configuration in a 50 W environment RFIN and RFOUT are both connected to DC ground Sample testing only www.onsemi.com 3 TCP−3027HA Representative performance data at 255C for 2.7 pF WLCSP Package Figure 3. 2nd Harmonic Power Figure 2. Capacitance Figure 4. 3rd Harmonic Power Figure 5. Q Table 3. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units Input Power +40 dBm Bias Voltage +25 (Note 6) V Operating Temperature Range −30 to +85 °C Storage Temperature Range −55 to +125 °C ESD − Human Body Model Class 1A JEDEC HBM Standard (Note 7) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 6. WLCSP: Recommended Bias Voltage not to exceed 20 V 7. Class 1A defined as passing 250 V, but may fail after exposure to 500 V ESD pulse www.onsemi.com 4 TCP−3027HA ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE The following assembly considerations should be observed: Table 4. Reflow Profile Chart Cleanliness Profile Feature Pb−Free Assembly These chips should be handled in a clean environment. Average ramp−up rate (Tsmax to Tp) 3°C / second max Mounting Preheat Temperature Min (Tsmin) Temperature Max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60−180 seconds The QFN PTIC is fabricated for Flip Chip solder mounting. The output pads are plated with pure tin, and the device is rated as MSL2. The PTIC QFN is RoHS-compliant and compatible with lead-free soldering profile. Time maintained above Temperature (TL) Time (tL) 217°C 60−150 seconds Electro-static Sensitivity ON Semiconductor’s PTICs are ESD Class 1A sensitive. The proper ESD handling procedures should be used. Peak Temperature (Tp) 260°C (maximum for the customer) Time within 5°C of actual Peak Temperature (tp)2 20−40 seconds Ramp−down Rate 6°C / second max Time 25°C to Peak Temperature 8 minutes max Figure 6. Reflow Profile ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES RF When configuring the PTIC in your specific circuit design, at least one of the RF terminals must be connected to DC ground. If minimum transition times are required, DC ground on both RF terminals is recommended. To minimize losses, the PTIC should be oriented such that RF2 is at the lower RF impedance of the two RF nodes. A shunt PTIC, for example, should have RF2 connected to RF ground. ANT RF1 (PTIC Pad) RF2 (PTIC Pad) Bias Figure 7. PTIC Orientation Functional Block Diagram www.onsemi.com 5 TCP−3027HA PART NUMBER DEFINITION Example: TCP−3027HA−QT TCP - 30 27 HA - Q T Product Family Process Status Process Generation Capacitor Value Tuning Package / Format Packing TCP “blank” = Production X = Pilot Production 10 = Gen 1.0 30 = Gen 3.0 31 = Gen 3.1 12 = 1.2 pF 18 = 1.8 pF 27 = 2.7 pF 33 = 3.3 pF 39 = 3.9 pF 47 = 4.7 pF 56 = 5.6 pF 68 = 6.8 pF 82 = 8.2 pF N = Normal H = High HA = High Linearity D = WLCSP Q = QFN T = T&R - S= Special/Custom P = Prototype - Table 5. PART NUMBERS Capacitance Part Number TCP-3027HA-QT 2V 20 V Package 2.70 0.675 6-Pin QFN www.onsemi.com 6 TCP−3027HA PACKAGE DIMENSIONS QFN6 1.6x1.2, 0.5P CASE 485DX ISSUE O D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. L L L1 PIN ONE IDENTIFIER 0.05 C 2X 2X ÍÍÍ ÍÍÍ ÍÍÍ 0.05 C DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS ÉÉ ÉÉ ÇÇ EXPOSED Cu TOP VIEW A DETAIL B 0.10 C DIM A A1 A3 b D E e L L1 MOLD CMPD MILLIMETERS MIN MAX 0.90 1.00 0.00 0.05 0.15 REF 0.22 0.28 1.60 BSC 1.20 BSC 0.50 BSC 0.39 0.46 −−− 0.15 DETAIL B ALTERNATE CONSTRUCTIONS A3 A1 0.05 C C SIDE VIEW RECOMMENDED MOUNTING FOOTPRINT* SEATING PLANE 6X 6X 0.60 b 0.10 C A PACKAGE OUTLINE B 0.03 C DETAIL A 1.40 1 1 6X 0.50 PITCH L 6X 0.30 DIMENSIONS: MILLIMETERS 2 B A *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. C e BOTTOM VIEW ParaScan is a trademark of Paratek Microwave, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative TCP−3027HA/D